Methods and apparatus for removing functional bugs and hardware trojans for integrated circuits implemented by field programmable gate array (FPGA)

1. A method executed by a computer system to transform the function of a programmable circuit for improving circuit functionality, the method comprising:

providing a lookup-table (LUT) mapped circuit representation derived from the programmable circuit being implemented with a first Register-Transfer Level (RTL) document, the first RTL document being of an original specification;

providing a second RTL document of the programmable circuit, the second RTL document being of a revised specification, wherein the revised specification is modified from the original specification and has a transformed function from the original specification;

converting the LUT mapped circuit representation into a shadow netlist, the shadow netlist corresponding to a first gate level (GTL) netlist representing the LUT mapped circuit representation;

generating a second GTL netlist from the second RTL document;

producing at least one engineering change order (ECO) patch to be completely merged inside the LUT mapped circuit representation based on a comparison of the shadow netlist with the second GTL netlist by identifying a list of LUTs in the programmable circuit to be modified; and

transforming, by the computer system and an ECO engine, the function of the programmable circuit by merging the at least one ECO patch inside the LUT mapped circuit representation, wherein the merged LUT mapped circuit representation is exactly functionally equivalent to the second GTL netlist to perform same functions such that the programmable circuit can be reprogrammed in accordance with the revised specification by making use of free merging cost property of LUT structures so as to reduce resource usage of the computer system in the transformation.

2. The method of claim 1 , wherein the producing step comprises:

comparing the shadow netlist with the second GTL netlist to obtain an ECO patch for at least one module to be ECOed and an insertion point in the LUT mapped circuit representation corresponding to the ECO patch;

locating the LUT containing the insertion point in the LUT mapped circuit representation for inserting the ECO patch;

determining whether the ECO patch can be completely merged inside the LUT containing the insertion point; and

in response to a determination that the ECO patch can be completely merged inside the LUT containing the insertion point, identifying the ECO patch ready to be merged inside the LUT mapped circuit representation.

3. The method of claim 2 , wherein the producing step further comprises:

in response to a determination that the ECO patch cannot be completely merged inside the LUT containing the insertion point, determining whether the ECO patch can be merged inside one or more empty LUTs; and

identifying the ECO patch ready to be merged inside the LUT mapped circuit representation in response to a determination that the ECO patch can be merged inside one or more empty LUTs.

4. The method of claim 2 , wherein the producing step further comprise:

in response to a determination that the ECO patch cannot be completely merged inside the LUT containing the insertion point,

applying disjoint support decomposition on the function of the ECO patch to decompose at least one sub-patch-function, wherein the at least one decomposed sub-patch-function has a variable support being a subset of the variable support of the LUT containing the insertion point;

merging the at least one sub-patch-function inside the LUT containing the insertion point;

updating the LUT mapped circuit representation and the shadow netlist; and

iteratively, obtaining a new ECO patch to be patched in the updated LUT mapped circuit representation by comparing the updated shadow netlist with the second GTL netlist until no more ECO patch is needed.

5. The method of claim 1 , wherein the producing step comprises:

comparing the shadow netlist with the second GTL netlist to obtain an ECO patch for at least one module to be ECOed and an insertion point in the LUT mapped circuit representation corresponding to the ECO patch;

locating the LUT containing the insertion point in the LUT mapped circuit representation for inserting the ECO patch;

determining whether the ECO patch can be completely merged inside one or more empty LUTs; and

in response to a determination that the ECO patch can be completely merged inside one or more empty LUTs, identifying the ECO patch ready to be merged inside the LUT mapped circuit representation.

6. The method of claim 1 , wherein the converting step further comprises:

recording a bit mask of each possible LUT6 and corresponding simplest logic expression; and

mapping the function of each LUT in the LUT mapped circuit representation into its equivalent sub-circuit to obtain a corresponding shadow netlist.

7. The method of claim 1 , further comprising:

applying incremental Placement and Routing (P&R);

generating the new bit stream based on the new P&R result; and

reprogramming the programmable circuit with the new bit stream.

8. A computer system for transforming the function of the programmable circuit for improving circuit functionality, the computer system comprising:

a hardware processor;

a non-transitory computer-readable storage medium having stored therein instructions that when executed cause the hardware processor to:

retrieve a lookup-table (LUT) mapped circuit representation from the programmable circuit being implemented with a first Register Transfer Level (RTL) document, the first RTL document being of an original specification;

obtain a second RTL document of the programmable circuit, the second RTL document being of a revised specification, wherein the revised specification is modified from the original specification and has a transformed function from the original specification;

convert the LUT mapped circuit representation into a shadow netlist, the shadow netlist corresponding to a first gate level (GTL) netlist representing the LUT mapped circuit representation;

generate a second GTL netlist from the second RTL document;

produce at least one engineering change order (ECO) patch to be completely merged inside the LUT mapped circuit representation based on a comparison of the shadow netlist with the second GTL netlist by identifying a list of LUTs in the programmable circuit to be modified; and

transform, along with an ECO engine, the function of the programmable circuit by merging the at least one ECO patch inside the LUT mapped circuit representation, wherein the merged LUT mapped circuit representation is exactly functionally equivalent to the second GTL netlist to perform same functions such that the programmable circuit can be reprogrammed in accordance with the revised specification by making use of free merging cost property of LUT structures so as to reduce resource usage of the computer system in the transformation.

9. The system of claim 8 , wherein the instructions when executed further cause the processor to:

compare the shadow netlist with the second GTL netlist to obtain an ECO patch for at least one module to be ECOed and an insertion point in the LUT mapped circuit representation corresponding to the ECO patch;

locate the LUT containing the insertion point in the LUT mapped circuit representation for inserting the ECO patch;

determine whether the ECO patch can be completely merged inside the LUT containing the insertion point; and

in response to a determination that the ECO patch can be completely merged inside the LUT containing the insertion point, identifying the ECO patch ready to be merged inside the LUT mapped circuit representation.

10. The system of claim 9 , wherein the instructions when executed further cause the processor to:

in response to a determination that the ECO patch cannot be completely merged inside the LUT containing the insertion point, determine whether the ECO patch can be merged inside one or more empty LUTs; and

in response to a determination that the ECO patch can be merged inside one or more empty LUT, identifying the ECO patch ready to be merged inside the LUT mapped circuit representation.

11. The system of claim 9 , wherein the instructions when executed further cause the processor to:

in response to a determination that the ECO patch cannot be completely merged inside the LUT containing the insertion point,

apply disjoint support decomposition on the function of the ECO patch to decompose at least one sub-patch-function, wherein the at least one decomposed sub-patch-function has a variable support being a subset of the variable support of the LUT containing the insertion point;

merge the at least one sub-patch-function inside the LUT containing the insertion point;

update the LUT mapped circuit representation and the shadow netlist; and

iteratively, obtain a new ECO patch to be patched in the updated LUT mapped circuit representation by comparing the updated shadow netlist with the second GTL netlist until no more ECO patch is needed.

12. The system of claim 8 , wherein the instructions when executed further cause the processor to:

compare the shadow netlist with the second GTL netlist to obtain an ECO patch for at least one module to be ECOed and an insertion point in the LUT mapped circuit representation corresponding to the ECO patch;

locate the LUT containing the insertion point in the LUT mapped circuit representation for inserting the ECO patch;

determine whether the ECO patch can be completely merged inside one or more empty LUTs; and

in response to a determination that the ECO patch can be completely merged inside one or more empty LUTs, identifying the ECO patch ready to be merged inside the LUT mapped circuit representation.

13. The system of claim 8 , wherein the instructions when executed further cause the processor to:

record a bit mask of each possible LUT6 and corresponding simplest logic expression; and

map the function of each LUT in the LUT mapped circuit representation into its equivalent sub-circuit to obtain a corresponding shadow netlist.

14. The system of claim 8 , wherein the instructions when executed further cause the processor to:

apply incremental P&R;

generate the new bit stream based on the new P&R result; and

reprogram the programmable circuit with the new bit stream.

15. A computer-implemented method that improves circuit functional iteration to transform the function of a programmable circuit, the method comprising:

receiving a lookup-table (LUT) mapped circuit representation derived from the programmable circuit being implemented with a first Register Transfer Level (RTL) document, the first RTL document being of an original specification;

receiving a second RTL document of the programmable circuit, the second RTL document being of a revised specification, wherein the revised specification is modified from the original specification and has a transformed function from the original specification;

converting the LUT mapped circuit representation into a shadow netlist, the shadow netlist corresponding to a first gate level (GTL) netlist representing LUT mapping for the LUT mapped circuit representation;

generating a second GTL netlist from the second RTL document;

producing at least one engineering change order (ECO) patch to be completely merged inside the LUT mapped circuit representation based on a comparison of the shadow netlist with the second GTL netlist by identifying a list of LUTs in the programmable circuit to be modified; and

transforming, by the computer system and an ECO engine, the function of the programmable circuit by merging the at least one ECO patch inside the LUT mapped circuit representation, wherein the merged LUT mapped circuit representation is exactly functionally equivalent to the second GTL netlist to perform same functions such that the programmable circuit can be reprogrammed in accordance with the revised specification by making use of free merging cost property of LUT structures so as to reduce resource usage of the computer system in the transformation.

16. The method of claim 15 , wherein the producing step comprises:

comparing the shadow netlist with the second GTL netlist to obtain an ECO patch for at least one module to be ECOed and an insertion point in the LUT mapped circuit representation corresponding to the ECO patch;

locating the LUT containing the insertion point in the LUT mapped circuit representation for inserting the ECO patch;

determining whether the ECO patch can be completely merged inside the LUT containing the insertion point; and

in response to a determination that the ECO patch can be completely merged inside the LUT containing the insertion point, identifying the ECO patch ready to be merged inside the LUT mapped circuit representation.

17. The method of claim 16 , wherein the producing step further comprises:

in response to a determination that the ECO patch cannot be completely merged inside the LUT containing the insertion point, determining whether the ECO patch can be merged inside one or more empty LUTs; and

identifying the ECO patch ready to be merged inside the LUT mapped circuit representation, in response to a determination that the ECO patch can be merged inside one or more empty LUTs.

18. The method of claim 17 , wherein the producing step further comprise:

in response to a determination that the ECO patch cannot be completely merged inside the LUT containing the insertion point,

applying disjoint support decomposition on the function of the ECO patch to decompose at least one sub-patch-function, wherein the at least one decomposed sub-patch-function has a variable support being a subset of the variable support of the LUT containing the insertion point;

merging the at least one sub-patch-function inside the LUT containing the insertion point;

updating the LUT mapped circuit representation and the shadow netlist; and

iteratively, obtaining a new ECO patch to be patched patch in the updated LUT mapped circuit representation by comparing the updated shadow netlist with the second GTL netlist until no more ECO patch is needed.

19. The method of claim 15 , wherein the producing step comprises:

comparing the shadow netlist with the second GTL netlist to obtain an ECO patch for at least one module to be ECOed and an insertion point in the LUT mapped circuit representation corresponding to the ECO patch;

locating the LUT containing the insertion point in the LUT mapped circuit representation for inserting the ECO patch;

determining whether the ECO patch can be completely merged inside one or more empty LUTs; and

in response to a determination that the ECO patch can be completely merged inside one or more empty LUTs, identifying the ECO patch ready to be merged inside the LUT mapped circuit representation.

20. The method of claim 15 , wherein the converting step further comprises:

recording a bit mask of each possible LUT6 and corresponding simplest logic expression; and

mapping the function of each LUT in the LUT mapped circuit representation into its equivalent sub-circuit to obtain a corresponding shadow netlist.