Air spacer and capping structures in semiconductor devices
A semiconductor device with air spacers and air caps and a method of fabricating the same are disclosed. The semiconductor device includes a substrate and a fin structure disposed on the substrate. The fin structure includes a first fin portion and a second fin portion. The semiconductor device further includes a source/drain (S/D) region disposed on the first fin portion, a contact structure disposed on the S/D region, a gate structure disposed on the second fin portion, an air spacer disposed between a sidewall of the gate structure and the contact structure, a cap seal disposed on the gate structure, and an air cap disposed between a top surface of the gate structure and the cap seal.
1. A semiconductor device, comprising:
a substrate;
a fin structure disposed on the substrate, wherein the fin structure comprises a first fin portion and a second fin portion;
a source/drain (S/D) region disposed on the first fin portion;
a contact structure disposed on the sir) region;
a gate structure disposed on the second fin portion;
an air spacer disposed between a sidewall of the gate structure and the contact structure;
a cap seal disposed on the gate structure; and
an air cap disposed between a top surface of the gate structure and the cap seal, wherein an air-filled cavity of the air cap is in contact with the top surface of the gate structure.
2. The semiconductor device of claim 1 , further comprising a spacer seal disposed between the cap seal and the air spacer.
3. The semiconductor device of claim 1 , further comprising a spacer seal disposed between the cap seal and the air cap.
4. The semiconductor device of claim 1 , further comprising an etch stop layer (ESL) disposed on the S/D region and along a sidewall of the contact structure, wherein the air spacer is disposed between the ESL and a sidewall of the gate structure.
5. The semiconductor device of claim 1 , further comprising a spacer with a first spacer portion disposed between the air spacer and the gate structure and a second spacer portion disposed on the SID region.
6. The semiconductor device of claim 1 , further comprising:
a via structure disposed on the contact structure; and
a spacer seal disposed on the air spacer, wherein top surfaces of the spacer seal and the via structure are substantially coplanar with each other.
7. The semiconductor device of claim 1 , further comprising:
a capping layer disposed on the contact structure; and
a spacer seal disposed on the air spacer, wherein top surfaces of the spacer seal and the capping layer are substantially coplanar with each other.
8. The semiconductor device of claim 1 , further comprising a spacer seal disposed between the sidewall of the gate structure and the contact structure, wherein the spacer seal surrounds the air spacer.
9. The semiconductor device of claim 1 , wherein a vertical dimension of the air spacer is greater than a vertical dimension of the gate structure.
10. The semiconductor device of claim 1 , further comprising a via structure disposed on the contact structure, wherein top surfaces of the cap seal and the via structure are substantially coplanar with each other.
11. A semiconductor device, comprising:
a substrate;
a fin structure with first and second fin portions disposed on the substrate;
a nanostructured channel region disposed on the first fin portion;
a gate-all-around (GAA) structure surrounding the nanostructured channel region;
a source/drain (S/D) region disposed on the second fin portion;
air interlayer dielectric (ILD) layer disposed on the S/D region;
an air spacer disposed between the gate structure and the ILD layer;
a cap seal disposed on the gate structure, wherein top surfaces of the cap seal and the ILD layer are substantially coplanar with each other; and
an air cap disposed between a top surface of the gate structure and the cap seat wherein an air-filled cavity of the air cap separates the top surface of the gate structure from a bottom surface of the cap seal.
12. The semiconductor device of claim 11 , further comprising a spacer seal with a first seal portion disposed between the cap seal and the ILD layer and a second seal portion disposed between the cap seal and the air spacer.
13. The semiconductor device of claim 11 , further comprising an etch stop layer (ESL) disposed along a sidewall of the ILD layer, wherein the air spacer is disposed between the ESL and the gate structure.
14. The semiconductor device of claim 11 , wherein a vertical dimension of the air cap is greater than a vertical dimension of the cap seal.
15. A semiconductor structure, comprising:
a substrate;
a fin structure disposed on the substrate, wherein the fin structure comprises a first fin portion and a second fin portion;
a source/drain (S/D) region disposed on the first fin portion;
a first dielectric layer disposed on the sir) region;
a gate structure disposed on the second fin portion;
a first air gap disposed between the gate structure and the first dielectric layer;
a second dielectric layer disposed on the gate structure; and
a second air gap disposed between a top surface of the gate structure and the second dielectric layer wherein the second air gap has a rectangular-shaped cross-sectional profile.
16. The semiconductor structure of claim 15 , further comprising a third dielectric layer disposed on the first air gap and between the gate structure and the first dielectric layer.
17. The semiconductor structure of claim 15 , further comprising a third dielectric layer disposed between the first air gap and the second dielectric layer.
18. The semiconductor structure of claim 15 , further comprising a third dielectric layer disposed on the first air gap and between the first dielectric layer and the second dielectric layer.
19. The semiconductor structure of claim 15 , wherein a vertical dimension of the first air gap is greater than a vertical dimension of the gate structure.
20. The semiconductor structure of claim 15 , further comprising a stack of semiconductor layers disposed on the second fin portion, wherein the gate structure surrounds each of the semiconductor layers.