Passivation scheme design for wafer singulation

1. A method of forming a semiconductor device, the method comprising:

forming first electrical components in a substrate in a first device region of the semiconductor device;

forming a first interconnect structure over and electrically coupled to the first electrical components;

forming a first passivation layer over the first interconnect structure, the first passivation layer extending from the first device region to a scribe line region adjacent to the first device region;

after forming the first passivation layer, removing the first passivation layer from the scribe line region while keeping a remaining portion of the first passivation layer in the first device region;

after removing the first passivation layer from the scribe line region, forming a conductive pad over the first passivation layer and electrically coupled to an electrically conductive feature of the first interconnect structure;

forming a second passivation layer over the conductive pad and over the first passivation layer, wherein the second passivation layer extends from the first device region to the scribe line region;

removing the second passivation layer from the scribe line region while keeping a remaining portion of the second passivation layer in the first device region; and

dicing along the scribe line region after removing the first second passivation layer.

2. The method of claim 1 , further comprising, before forming the first passivation layer, forming a first seal ring in a first seal ring region between the first device region and the scribe line region.

3. The method of claim 2 , wherein after removing the first passivation layer from the scribe line region, the first seal ring region remain remains covered by the first passivation layer.

4. The method of claim 1 , wherein the dicing is performed along a dicing path in the scribe line region, wherein a width of the dicing path is smaller than a width of the scribe line region.

5. The method of claim 1 , wherein the dicing forms a recess in the substrate, wherein a bottom of the recess is between a first side of the substrate facing the first interconnect structure and a second side of the substrate opposing the first side of the substrate.

6. The method of claim 5 , wherein the dicing is performed using a plasma dicing process.

7. The method of claim 5 , further comprising, after the dicing, reducing a thickness of the substrate from the second side of the substrate, wherein after reducing the thickness of the substrate, the recess extends through the substrate.

8. The method of claim 1 , wherein after removing the second passivation layer from the scribe line region, a first sidewall of the first passivation layer facing the scribe line region and a second sidewall of the second passivation layer facing the scribe line region are aligned along a same line.

9. The method of claim 1 , wherein after removing the second passivation layer from the scribe line region, a first sidewall of the first passivation layer facing the scribe line region is closer to the scribe line region than a second sidewall of the second passivation layer facing the scribe line region.

10. The method of claim 1 , wherein after removing the second passivation layer from the scribe line region, a first sidewall of the first passivation layer facing the scribe line region is further from the scribe line region than a second sidewall of the second passivation layer facing the scribe line region.

11. The method of claim 1 , further comprising:

forming second electrical components in the substrate in a second device region of the semiconductor device, the scribe line region being between the first device region and the second device region; and

forming a second interconnect structure over and electrically coupled to the second electrical components,

wherein forming the first passivation layer comprising forming the first passivation layer to extend continuously from the first device region to the second device region, wherein after removing the first passivation layer from the scribe line region, the first passivation layer covers an upper surface of the first interconnect structure and covers an upper surface of the second interconnect structure.

12. A method of forming a semiconductor device, the method comprising:

forming a first interconnect structure and a second interconnect structure over a substrate in a first device region and a second device region of the semiconductor device, respectively, wherein a scribe line region of the semiconductor device is interposed between the first device region and the second device region;

forming a first passivation layer over the first interconnect structure and over the second interconnect structure, wherein the first passivation layer extends continuously from the first device region to the second device region;

removing a first portion of the first passivation layer from the scribe line region;

after removing the first portion of the first passivation layer, forming a second passivation layer over the first passivation layer, the second passivation layer extending continuously from the first device region to the second device region;

removing a second portion of the second passivation layer from the scribe line region; and

after removing the second portion of the second passivation layer from the scribe line region, performing a plasma dicing process to form a trench in the scribe line region that extends into the substrate from a first side of the substrate facing the first passivation layer.

13. The method of claim 12 , wherein the first passivation layer is formed of a nitride-containing material.

14. The method of claim 12 , wherein a depth of the trench into the substrate is less than a thickness of the substrate.

15. The method of claim 14 , wherein the method further comprises, after performing the plasma dicing process, reducing the thickness of the substrate from a second side of the substrate facing away from the first passivation layer such that the trench extends through the substrate.

16. The method of claim 12 , wherein after removing the second portion of the second passivation layer, a first sidewall of the first passivation layer facing the scribe line region has a first distance from the scribe line region, and a second sidewall of the second passivation layer closest to the first sidewall has a second distance from the scribe line region, wherein the first distance is different from the second distance.

17. The method of claim 12 , further comprising, before forming the first passivation layer:

forming a first seal ring in a first seal ring region between the first device region and the scribe line region; and

forming a second seal ring in a second seal ring region between the second device region and the scribe line region.

18. The method of claim 17 , wherein the first seal ring and the second seal ring are covered by the first passivation layer and the second passivation layer during the plasma dicing process.

19. A method of forming a semiconductor device, the method comprising:

forming electrical components in a substrate;

forming an interconnect structure over the substrate and electrically coupled to the electrical components;

forming a seal ring around the interconnect structure;

forming a first passivation layer over the interconnect structure, over the seal ring, and over a dicing region of the semiconductor device adjacent to the seal ring;

removing a portion of the first passivation layer from the dicing region;

after removing the portion of the first passivation layer, forming a conductive pad over the first passivation layer;

forming a dielectric layer over the conductive pad, over the first passivation layer, and over the dicing region; and

after forming the dielectric layer, forming a trench in the dicing region using a plasma dicing process, wherein the trench is formed to extends from the dielectric layer into the substrate, wherein after the trench is formed, there is a first lateral distance between a first sidewall of the first passivation layer facing the trench and a sidewall of the dielectric layer closest to the first sidewall.

20. The method of claim 19 , further comprising after removing the portion of the first passivation layer and before forming the dielectric layer:

forming a second passivation layer over the conductive pad, over the first passivation layer, and over the dicing region; and

removing a portion of the second passivation layer from the dicing region, wherein after forming the trench, there is a second lateral distance between a second sidewall of the second passivation layer facing the trench and the sidewall of the dielectric layer, wherein the first lateral distance is different from the second lateral distance.