Semiconductor device including resistor element

1. A semiconductor device comprising:

a first pad defined on one surface of a first chip, the first chip includes a memory cell array disposed in a cell region and a first peripheral circuit disposed in a peripheral region outside of the cell region;

a second pad defined on one surface of a second chip, which is stacked on the first chip, and bonded to the first pad, the second chip includes a second peripheral circuit disposed in the peripheral region;

a first resistor element defined in the first chip and coupled to the first pad; and

a second resistor element defined in the second chip and coupled to the second pad,

wherein the first resistor element and the second resistor element are disposed between the first peripheral circuit and the second peripheral circuit in the peripheral region,

wherein at least a portion of the first resistor element and at least a portion of the second resistor element overlap each other in a first direction that is perpendicular to the one surface of the first chip and the one surface of the second chip.

2. The semiconductor device according to claim 1 , further comprising:

a third pad disposed on the one surface of the first chip and coupled to the memory cell array;

a row decoder and a page buffer circuit defined in the second chip; and

a fourth pad disposed on the one surface of the second chip, coupled to one of the row decoder and the page buffer circuit, and bonded to the third pad.

3. The semiconductor device according to claim 1 , further comprising:

a resistor including the first resistor element, the first pad, the second pad and the second resistor element connected in series.

4. The semiconductor device according to claim 1 ,

wherein the first resistor element comprises a plurality of first vertical resistor patterns, defined in the first chip and coupled to first pads, extending in the first direction;

wherein the second resistor element comprises a plurality of second vertical resistor patterns, defined in the second chip and coupled to second pads, extending in the first direction, and

wherein the plurality of first vertical resistor patterns correspond to the plurality of second vertical resistor patterns.

5. The semiconductor device according to claim 4 ,

wherein the plurality of first vertical resistor patterns overlap with the corresponding plurality of second vertical resistor patterns in the vertical direction.

6. The semiconductor device according to claim 5 , further comprising a first wiring line defined in the first chip and a second wiring line defined in the second chip, and

the plurality of first vertical resistor patterns, the plurality of second vertical resistor patterns, the plurality of first pads, the plurality of second pads, the first wiring line and the second wiring line are coupled in series while forming a snake-like shape with a baseline at an interface of the first chip and the second chip.

7. The semiconductor device according to claim 4 , further comprising

a plurality of first vertical resistor patterns overlapping with a corresponding plurality of second vertical resistor patterns in the vertical direction.

8. The semiconductor device according to claim 7 , further comprising a first wiring line defined in the first chip and a second wiring line defined in the second chip, and

the plurality of first vertical resistor patterns, the plurality of second vertical resistor patterns, the plurality of first pads, the plurality of second pads, the first wiring line and the second wiring line are coupled in series while forming a square wave-like shape with a baseline at an interface of the first chip and the second chip.

9. A semiconductor device comprising:

a first pad defined on one surface of a first chip, the first chip includes a memory cell array disposed in a cell region and a first peripheral circuit disposed in a peripheral region outside of the cell region;

a second pad defined on one surface of a second chip, which is stacked on the first chip in a first direction, and bonded to the first pad, the second chip includes a second peripheral circuit in the peripheral region;

a first vertical resistor pattern, defined in the first chip and coupled to the first pad, extending in the first direction; and

a second vertical resistor pattern defined in the second chip and coupled to the second pad, extending in the first direction,

wherein the first vertical resistor pattern and the second vertical resistor pattern are disposed between the first peripheral circuit and the second peripheral circuit in the peripheral region, and

wherein at least a portion of the first vertical resistor pattern and at least a portion of the second vertical resistor pattern overlap each other in a first direction that is perpendicular to the one surface of the first chip and the one surface of the second chip.

10. The semiconductor device according to claim 9 , further comprising:

wherein the first vertical resistor pattern overlaps with at least one of the first peripheral circuit and the second peripheral circuit in the first direction.

11. The semiconductor device according to claim 9 , further comprising:

wherein the second vertical resistor pattern overlaps with at least one of the first peripheral circuit and the second peripheral circuit in the first direction.

12. The semiconductor device according to claim 9 , further comprising:

a resistor including the first resistor pattern, the first pad, the second pad and the second resistor pattern connected in series.