Apparatuses and methods for providing refresh addresses

1. An apparatus comprising:

a plurality of address registers each configured to store a row address;

a plurality of counter circuits each configured to store a count value corresponding to an associated one of the plurality of address registers;

a comparing circuit configured to determine a counter circuit of the plurality of counter circuits storing a highest count value; and

a control logic circuit configured to control the comparing circuit to determine the counter circuit of the plurality of counter circuits storing the highest count value responsive to a precharge command received by the apparatus.

2. The apparatus of claim 1 , wherein the control logic circuit is configured to provide a selection signal to the comparing circuit, wherein the comparing circuit is configured to determine the counter circuit of the plurality of counter circuits storing the highest count value responsive to the selection signal transitioning from a first state to a second state, wherein the control logic circuit is configured to transition the selection signal from the first state to the second state based, at least in part, on the precharge command.

3. The apparatus of claim 2 , wherein the comparing circuit is further configured to determine a counter circuit of the plurality of counter circuits storing a lowest count value responsive to the selection signal transitioning from the second state to the first state, wherein the control logic circuit is configured to transition the selection signal from the second state to the first state based, at least in part, on an activation command received by the apparatus.

4. The apparatus of claim 3 , further comprising a sample generator circuit configured to provide a sampling signal to the comparing circuit, wherein the comparing circuit is further configured to determine the counter circuit of the plurality of counter circuits storing the lowest count value responsive to activation of the timing control signal.

5. The apparatus of claim 1 , further comprising a storage control circuit coupled to the comparing circuit, the storage control circuit comprising a pointer, wherein the pointer stores a value indicating an address register of the plurality of address registers associated with the counter circuit storing the highest count value determined by the comparing circuit.

6. The apparatus of claim 5 , further comprising an address convertor, wherein the storage control circuit is configured to cause a row address stored in the address register of the plurality of address registers associated with the counter circuit storing the highest count value to be provided to the address convertor, wherein the address convertor is configured to generate one or more refresh addresses based, at least in part, on the row address.

7. The apparatus of claim 2 , wherein the control logic circuit is configured to receive an activation signal and a refresh signal wherein the control logic circuit is configured to provide the selection signal in the first state when the activation signal is in an active state and the refresh signal is in an inactive state.

8. The apparatus of claim 7 , further comprising a command control circuit configured to provide the activation signal and the refresh signal.

9. A method comprising:

receiving a precharge command at a memory; and

responsive, at least in part, to the precharge command, determining with a count comparing circuit, a counter circuit of a plurality of counter circuits storing a highest count value.

10. The method of claim 9 , further comprising:

providing a row address from an address register associated with the counter circuit of the plurality of counter circuits storing the highest count value;

generating at least one refresh address based, at least in part, on the row address; and

responsive, at least in part, to a refresh command and the active refresh state signal, refreshing at least one word line corresponding to the at least one refresh address.

11. The method of claim 9 , further comprising transitioning a selection signal from a first state to a second state responsive, at least in part, to the precharge command, wherein determining with the count comparing circuit, the counter circuit of the plurality of counter circuits storing a highest count value is performed responsive to the transitioning.

12. The method of claim 11 , further comprising:

receiving an activation command;

responsive, at least in part, to the activation command, transitioning the selection signal from the first state to the second state; and

responsive, at least in part, to the transitioning of the selection signal from the first state to the second state, determining with the count comparing circuit, a counter circuit of the plurality of counter circuits storing a lowest count value.

13. The method of claim 12 , further comprising:

receiving an active timing control signal; and

responsive, at least in part, to the active timing control signal, determining with the count comparing circuit, the counter circuit of the plurality of counter circuits storing the lowest count value.

14. The method of claim 13 , further comprising, responsive, at least in part, to the active timing control signal:

comparing, with an address comparing circuit, a sampled row address to a plurality of row addresses stored in a corresponding one of a plurality of address registers;

storing in an address register of the plurality of address registers associated with the counter circuit of the plurality of counter circuits storing the lowest count value when the sampled row address does not match the plurality of row addresses; and

when the sampled row address matches a row address of the plurality of row addresses, incrementing a counter circuit of the plurality of counter circuits associated with an address register of the plurality of address registers storing the row address of the plurality of row addresses.

15. The method of claim 13 , wherein the active timing control signal is provided a plurality of times during a time period between the activation command and the precharge command and the count comparing circuit determines the counter circuit of the plurality of counter circuits storing the lowest count value each time the active timing control signal is provided.

16. The method of claim 9 , further comprising performing a row hammer refresh operation responsive to a refresh command and the active refresh state signal.

17. A method comprising:

receiving a signal;

receiving an active refresh state signal, wherein the active refresh state signal is associated with a row hammer refresh operation;

responsive, at least in part, to the signal determining a counter circuit of a plurality of counter circuits storing a highest count value, wherein the determining is performed by a count comparing circuit responsive to a transition of a selection signal provided by a control logic circuit, wherein the transition of the selection signal is made responsive to the signal, wherein the signal is a precharge command; and

providing, on an address bus, a row address from an address register associated with the counter circuit.

18. The method of claim 17 , further comprising:

generating a refresh address based on the row address; and

providing the refresh address on a second address bus.

19. The method of claim 18 , further comprising:

receiving a refresh command; and

responsive, at least in part, to the refresh command and the active refresh state signal, refreshing a word line corresponding to the refresh address.