Suspect resolution for scan chain defect diagnosis
This application discloses a computing system implementing an automatic test pattern generation tool to perform scan chain diagnosis-driven compaction setting. The computing system can perform fault simulation on scan chains in a circuit design describing an integrated circuit, which loads test patterns to the simulated scan chains and unloads test responses from the simulated scan chains. The computing system can determine locations of sensitive bits and locations of unknown bits in each of the scan chains based on the test responses from the simulated scan chains, and generate a configuration for a compactor in the integrated circuit based, at least in part, on the locations of the sensitive bits and the locations of the unknown bits in each of the scan chains, wherein the compactor is configured to compact test responses from the scan chains in the integrated circuit based on the configuration.
1. A method comprising:
performing, by a computing system, fault simulation on scan chains in a circuit design describing an integrated circuit, which loads test patterns to the simulated scan chains and unloads test responses from the simulated scan chains;
determining, by the computing system, locations of sensitive bits and locations of unknown bits in each of the scan chains based on the test responses from the simulated scan chains; and
generating, by the computing system, a configuration for a compactor in the integrated circuit based, at least in part, on the locations of the sensitive bits and the locations of the unknown bits in each of the scan chains, wherein the compactor is configured to compact test responses from the scan chains in the integrated circuit based on the configuration.
2. The method of claim 1 , wherein the compactor utilizes the configuration to selectively mask the test responses from the scan chains in the integrated circuit during a compaction of the test responses for output from the integrated circuit.
3. The method of claim 1 , further comprising identifying, by the computing system, masked sensitive bits corresponding the sensitive bits that would be masked during compaction of the test responses based, at least in part, on the locations of the sensitive bits and the locations of the unknown bits in each of the scan chains.
4. The method of claim 3 , further comprising determining, by the computing system, a difference between a total number of the sensitive bits and a total number of masked sensitive bits for each of the scan chains, wherein generating the configuration for the compactor in the integrated circuit is based, at least in part, on the difference between the total number of the sensitive bits and a total number of masked sensitive bits for each of the scan chains.
5. The method of claim 4 , further comprising selecting, by the computing system, one of the scan chains to set in the configuration based on a magnitude of the difference between the total number of the sensitive bits and a total number of masked sensitive bits for each of the scan chains.
6. The method of claim 4 , further comprising setting, by the computing system, one of the scan chains to set to masked in the configuration based on a polarity of the difference between the total number of the sensitive bits and a total number of masked sensitive bits for each of the scan chains.
7. The method of claim 1 , wherein the compactor is at least one of a combination compactor to compact the test responses spatially based on the configuration, a finite input response compactor to compact the test responses through convolution based on the configuration, or an infinite input response compactor to compact the test responses temporally based on the configuration.
8. A system comprising:
a memory system configured to store computer-executable instructions; and
a computing system, in response to execution of the computer-executable instructions, is configured to:
perform fault simulation on scan chains in a circuit design describing an integrated circuit, which loads test patterns to the simulated scan chains and unloads test responses from the simulated scan chains;
determine locations of sensitive bits and locations of unknown bits in each of the scan chains based on the test responses from the simulated scan chains; and
generate a configuration for a compactor in the integrated circuit based, at least in part, on the locations of the sensitive bits and the locations of the unknown bits in each of the scan chains, wherein the compactor is configured to compact test responses from the scan chains in the integrated circuit based on the configuration.
9. The system of claim 8 , wherein the compactor utilizes the configuration to selectively mask the test responses from the scan chains in the integrated circuit during a compaction of the test responses for output from the integrated circuit.
10. The system of claim 8 , wherein the computing system, in response to execution of the computer-executable instructions, is further configured to identify masked sensitive bits corresponding the sensitive bits that would be masked during compaction of the test responses based, at least in part, on the locations of the sensitive bits and the locations of the unknown bits in each of the scan chains.
11. The system of claim 10 , wherein the computing system, in response to execution of the computer-executable instructions, is further configured to:
determine a difference between a total number of the sensitive bits and a total number of masked sensitive bits for each of the scan chains; and
generate the configuration for the compactor in the integrated circuit based, at least in part, on the difference between the total number of the sensitive bits and a total number of masked sensitive bits for each of the scan chains.
12. The system of claim 11 , wherein the computing system, in response to execution of the computer-executable instructions, is further configured to select one of the scan chains to set in the configuration based on a magnitude of the difference between the total number of the sensitive bits and a total number of masked sensitive bits for each of the scan chains.
13. The system of claim 11 , wherein the computing system, in response to execution of the computer-executable instructions, is further configured to set one of the scan chains to set to masked in the configuration based on a polarity of the difference between the total number of the sensitive bits and a total number of masked sensitive bits for each of the scan chains.
14. An apparatus comprising at least one computer-readable memory device storing instructions configured to cause one or more processing devices to perform operations comprising:
performing, by a computing system, fault simulation on scan chains in a circuit design describing an integrated circuit, which loads test patterns to the simulated scan chains and unloads test responses from the simulated scan chains;
determining, by the computing system, locations of sensitive bits and locations of unknown bits in each of the scan chains based on the test responses from the simulated scan chains; and
generating, by the computing system, a configuration for a compactor in the integrated circuit based, at least in part, on the locations of the sensitive bits and the locations of the unknown bits in each of the scan chains, wherein the compactor is configured to compact test responses from the scan chains in the integrated circuit based on the configuration.
15. The apparatus of claim 14 , wherein the compactor utilizes the configuration to selectively mask the test responses from the scan chains in the integrated circuit during a compaction of the test responses for output from the integrated circuit.
16. The apparatus of claim 14 , wherein the instructions are configured to cause one or more processing devices to perform operations further comprising identifying masked sensitive bits corresponding the sensitive bits that would be masked during compaction of the test responses based, at least in part, on the locations of the sensitive bits and the locations of the unknown bits in each of the scan chains.
17. The apparatus of claim 16 , wherein the instructions are configured to cause one or more processing devices to perform operations further comprising:
determining a difference between a total number of the sensitive bits and a total number of masked sensitive bits for each of the scan chains; and
generating the configuration for the compactor in the integrated circuit based, at least in part, on the difference between the total number of the sensitive bits and a total number of masked sensitive bits for each of the scan chains.
18. The apparatus of claim 17 , wherein the instructions are configured to cause one or more processing devices to perform operations further comprising selecting one of the scan chains to set in the configuration based on a magnitude of the difference between the total number of the sensitive bits and a total number of masked sensitive bits for each of the scan chains.
19. The apparatus of claim 17 , wherein the instructions are configured to cause one or more processing devices to perform operations further comprising setting one of the scan chains to set to masked in the configuration based on a polarity of the difference between the total number of the sensitive bits and a total number of masked sensitive bits for each of the scan chains.
20. The apparatus of claim 14 , wherein the compactor is at least one of a combination compactor to compact the test responses spatially based on the configuration, a finite input response compactor to compact the test responses through convolution based on the configuration, or an infinite input response compactor to compact the test responses temporally based on the configuration.