Estimating integrated circuit yield from modeled response to scaling of distribution samples

1. A method comprising:

performing, by a computing system, scaled sampling of parameter values in a foundry model describing parameter variations for a manufacturing process capable of fabricating an integrated circuit described in a circuit design, wherein the scaled sampling of the parameter values includes:

scaling a distribution of the parameter values in the foundry model, which expands the distribution of the parameter values in the foundry model so that the scaled distribution of the parameter values has a larger standard deviation than the distribution of the parameter values in the foundry model, and

selecting samples of the parameter values from the scaled distribution;

simulating, by the computing system, the circuit design with the scaled samples of the parameter values;

building, by the computing system, a geometric model to describe a response of the circuit design to the scaled samples of the parameter values, wherein the geometric model is configured to include one or more failure regions corresponding to geometric descriptions for failures of the circuit design to meet a specification during simulation with the scaled samples of the parameter values; and

estimating, by the computing system, a yield for an output of the integrated circuit described by the circuit design based on the geometric mode describing the response of the circuit design to the scaled samples of the parameter values during the simulation.

2. The method of claim 1 , wherein estimating the yield for the output of the circuit design further comprises:

measuring distances to the failure regions in the geometric model, which corresponds to probabilities of failure for the failure regions; and

extrapolating a probability of failure for the output of the integrated circuit from the measured distances to the failure regions in the geometric model, wherein the probability of failure for the output of the integrated circuit corresponds to the yield for the output of the circuit design.

3. The method of claim 1 , wherein building the geometric model further comprises:

applying the response of the circuit design to the scaled samples of the parameter values to multiple geometric models; and

selecting one of the geometric models based, at least in part, on a maximum likelihood estimation used to determine a fit of the response of the circuit design to the multiple geometric models.

4. The method of claim 1 , wherein the scaled sampling of the parameter values is performed with different levels of scaling, and wherein the simulating of the circuit design is performed with the scaled samples of the parameter values having the different levels of the scaling.

5. The method of claim 1 , wherein the foundry model includes a probability distribution for occurrences of the parameter values during the manufacturing process.

6. A system comprising:

a memory system configured to store computer-executable instructions; and

a computing system, in response to execution of the computer-executable instructions, is configured to:

perform scaled sampling of parameter values in a foundry model describing parameter variations for a manufacturing process capable of fabricating an integrated circuit described in a circuit design, wherein the scaled sampling of the parameter values includes:

scaling a distribution of the parameter values in the foundry model, which expands the distribution of the parameter values in the foundry model so that the scaled distribution of the parameter values has a larger standard deviation than the distribution of the parameter values in the foundry model, and

selecting samples of the parameter values from the scaled distribution;

simulate the circuit design with the scaled samples of the parameter values;

build a geometric model to describe a response of the circuit design to the scaled samples of the parameter values, wherein the geometric model is configured to include one or more failure regions corresponding to geometric descriptions for failures of the circuit design to meet a specification during simulation with the scaled samples of the parameter values; and

estimate a yield for an output of the integrated circuit described by the circuit design based on the geometric mode describing the response of the circuit design to the scaled samples of the parameter values during the simulation.

7. The system of claim 6 , wherein the computing system, in response to execution of the computer-executable instructions, is further configured to estimate the yield for the output of the circuit design by:

measuring distances to the failure regions in the geometric model, which corresponds to probabilities of failure for the failure regions; and

extrapolating a probability of failure for the output of the integrated circuit from the measured distances to the failure regions in the geometric model, wherein the probability of failure for the output of the integrated circuit corresponds to the yield for the output of the circuit design.

8. The system of claim 6 , wherein the computing system, in response to execution of the computer-executable instructions, is further configured to build the geometric model by:

applying the response of the circuit design to the scaled samples of the parameter values to multiple geometric models; and

selecting one of the geometric models based, at least in part, on a maximum likelihood estimation used to determine a fit of the response of the circuit design to the multiple geometric models.

9. The system of claim 6 , wherein the computing system, in response to execution of the computer-executable instructions, is further configured to perform scaled sampling of the parameter values with different levels of scaling, and simulate the circuit design with the scaled samples of the parameter values having the different levels of scaling.

10. An apparatus comprising at least one computer-readable memory device storing instructions configured to cause one or more processing devices to perform operations comprising:

performing scaled sampling of parameter values in a foundry model describing parameter variations for a manufacturing process capable of fabricating an integrated circuit described in a circuit design, wherein the scaled sampling of the parameter values includes:

scaling a distribution of the parameter values in the foundry model, which expands the distribution of the parameter values in the foundry model so that the scaled distribution of the parameter values has a larger standard deviation than the distribution of the parameter values in the foundry model, and

selecting samples of the parameter values from the scaled distribution;

simulating the circuit design with the scaled samples of the parameter values;

building a geometric model to describe a response of the circuit design to the scaled samples of the parameter values, wherein the geometric model is configured to include one or more failure regions corresponding to geometric descriptions for failures of the circuit design to meet a specification during simulation with the scaled samples of the parameter values; and

estimating a yield for an output of the integrated circuit described by the circuit design based on the geometric mode describing the response of the circuit design to the scaled samples of the parameter values during the simulation.

11. The apparatus of claim 10 , wherein the instructions are configured to cause one or more processing devices to perform operations further comprising estimating the yield for the output of the circuit design by:

measuring distances to the failure regions in the geometric model, which corresponds to probabilities of failure for the failure regions; and

extrapolating a probability of failure for the output of the integrated circuit from the measured distances to the failure regions in the geometric model, wherein the probability of failure for the output of the integrated circuit corresponds to the yield for the output of the circuit design.

12. The apparatus of claim 10 , wherein the instructions are configured to cause one or more processing devices to perform operations further comprising building the geometric model by:

applying the response of the circuit design to the scaled samples of the parameter values to multiple geometric models; and

selecting one of the geometric models based, at least in part, on a maximum likelihood estimation used to determine a fit of the response of the circuit design to the multiple geometric models.

13. The apparatus of claim 10 , wherein the instructions are configured to cause one or more processing devices to perform operations further comprising performing the scaled sampling of the parameter values with different levels of scaling, and simulating the circuit design with the scaled samples of the parameter values having the different levels of the scaling.

14. The apparatus of claim 10 , wherein the foundry model includes a probability distribution for occurrences of the parameter values during the manufacturing process.