Semiconductor device

1. A semiconductor device, comprising:

a first semiconductor fin comprising a first channel region;

a second semiconductor fin comprising a second channel region;

a first gate structure on the first channel region, wherein the first gate structure comprises a first silicon oxide layer on the first channel region, a first high-k dielectric layer on the first silicon oxide layer, and a first metal gate on the first high-k dielectric layer, wherein a top surface of the first silicon oxide layer is in direct contact with the first high-k dielectric layer; and

a second gate structure on the second channel region, wherein the second gate structure comprises a second silicon oxide layer on the second channel region, a second high-k dielectric layer on the second silicon oxide layer, and a second metal gate on the second high-k dielectric layer, wherein the first silicon oxide layer has a Si 4+ ion concentration greater than a Si 4+ ion concentration of a bottom portion of the second silicon oxide layer, and a top surface of the second silicon oxide layer is in direct contact with the second high-k dielectric layer.

2. The semiconductor device of claim 1 , wherein the first silicon oxide layer has a thickness less than a thickness of the second silicon oxide layer.

3. The semiconductor device of claim 1 , wherein the first silicon oxide layer has a thickness less than a thickness of the first high-k dielectric layer.

4. The semiconductor device of claim 1 , wherein the first silicon oxide layer is substantially pin-hole free.

5. The semiconductor device of claim 1 , wherein the first high-k dielectric layer is substantially pin-hole free.

6. The semiconductor device of claim 1 , wherein a top surface of the first high-k dielectric layer is lower than a top surface of the second high-k dielectric layer.

7. The semiconductor device of claim 6 , wherein a top surface of the first metal gate is substantially coplanar with a top surface of the second metal gate.

8. The semiconductor device of claim 1 , wherein a height of the first metal gate is greater than a height of the second metal gate.

9. A semiconductor device, comprising:

a substrate comprising a first channel region and a second channel region;

a first gate structure on the first channel region, wherein the first gate structure comprises a first silicon oxide layer on the first channel region, a first high-k dielectric layer on and in direct contact with the first silicon oxide layer, and a first metal gate on the first high-k dielectric layer; and

a second gate structure on the second channel region, wherein the second gate structure comprises a second silicon oxide layer on the second channel region, a second high-k dielectric layer on and in direct contact with the second silicon oxide layer, and a second metal gate on the second high-k dielectric layer, wherein a Si 4+ ion concentration of the first silicon oxide layer is higher than a Si 4+ ion concentration of the second silicon oxide layer, and the second silicon oxide layer is thicker than the second high-k dielectric layer.

10. The semiconductor device of claim 9 , wherein the first silicon oxide layer is substantially pin-hole free.

11. The semiconductor device of claim 9 , wherein the second silicon oxide layer is at least six times thicker than the first silicon oxide layer.

12. The semiconductor device of claim 9 , wherein the first silicon oxide layer is thinner than the first high-k dielectric layer.

13. The semiconductor device of claim 9 , wherein the first high-k dielectric layer and the second high-k dielectric layer have substantially a same thickness.

14. A semiconductor device, comprising:

a substrate comprising a first semiconductor fin and a second semiconductor fin;

an isolation region in the substrate and laterally surrounding a lower portion of the first semiconductor fin;

a liner between the isolation region and the first semiconductor fin;

a first gate structure over a first portion of the first semiconductor fin, wherein the first gate structure comprises an interfacial layer on the first semiconductor fin, a first high-k dielectric layer on the interfacial layer, and a first metal gate on the first high-k dielectric layer;

a first source/drain region over a second portion of the first semiconductor fin;

a second gate structure over a first portion of the second semiconductor fin, wherein the second gate structure comprises a gate oxide layer on the second semiconductor fin, a second high-k dielectric layer on the gate oxide layer, and a second metal gate on the second high-k dielectric layer, wherein the interfacial layer has a Si 4+ ion concentration greater than a Si 4+ ion concentration of the gate oxide layer, and the liner is in direct contact with the first high-k dielectric layer and spaced apart from the second high-k dielectric layer; and

a second source/drain region over a second portion of the second semiconductor fin.

15. The semiconductor device of claim 14 , wherein the liner is in contact with the interfacial layer.

16. The semiconductor device of claim 14 , wherein the liner is in contact with a sidewall of the first semiconductor fin.

17. The semiconductor device of claim 14 , wherein a thickness of the gate oxide layer is greater than a thickness of the interfacial layer.

18. The semiconductor device of claim 14 , wherein a thickness of the gate oxide layer is greater than a thickness of the liner.

19. The semiconductor device of claim 14 , wherein the liner is in contact with the interfacial layer and the gate oxide layer.

20. The semiconductor device of claim 14 , wherein the liner is in contact with a sidewall of the first semiconductor fin and a sidewall of the second semiconductor fin.