IP Library › Granted Patent US 11,360,914
Granted Patent B2
US 11,360,914 · App. 17/008,991 · Granted Jun 14, 2022

Apparatus and method for memory management in a graphics processing environment

Inventors: Niranjan L. Cooray (Folsom, CA); Abhishek R. Appu (El Dorado Hills, CA); Altug Koker (El Dorado Hills, CA); Joydeep Ray (Folsom, CA); Balaji Vembu (Folsom, CA); Pattabhiraman K (Bangalore, IN); David Puffer (Tempe, AZ); David J. Cowperthwaite (Portland, OR); Rajesh M. Sankaran (Portland, OR); Satyeshwar Singh (Mather, CA); Sameer Kp (Bangalore, IN); Ankur N. Shah (Folsom, CA); Kun Tian (Atlanta, GA)
Assignee: Intel Corporation
G06F13/16G06F12/0802G06F12/1009G06F12/1027G06F12/1036G06F13/4068G06F2212/1024G06F2212/302G06F2212/60G06F2212/68
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Quick Facts
Patent No.
US 11,360,914
App. No.
17/008,991
Granted
Jun 14, 2022
Kind
B2
Abstract

An apparatus and method are described for implementing memory management in a graphics processing system. For example, one embodiment of an apparatus comprises: a first plurality of graphics processing resources to execute graphics commands and process graphics data; a first memory management unit (MMU) to communicatively couple the first plurality of graphics processing resources to a system-level MMU to access a system memory; a second plurality of graphics processing resources to execute graphics commands and process graphics data; a second MMU to communicatively couple the second plurality of graphics processing resources to the first MMU; wherein the first MMU is configured as a master MMU having a direct connection to the system-level MMU and the second MMU comprises a slave MMU configured to send memory transactions to the first MMU, the first MMU either servicing a memory transaction or sending the memory transaction to the system-level MMU on behalf of the second MMU.

Claims (6)

1. An apparatus comprising:

a first plurality of graphics processing resources to execute graphics commands and process graphics data;

a first memory management unit (MMU) to communicatively couple the first plurality of graphics processing resources to a system-level MMU to access a system memory;

a second plurality of graphics processing resources to execute graphics commands and process graphics data;

a second MMU to communicatively couple the second plurality of graphics processing resources to the first MMU;

wherein the first MMU is configured as a master MMU having a direct connection to the system-level MMU and the second MMU comprises a slave MMU configured to send memory transactions to the first MMU, the first MMU either servicing a memory transaction or sending the memory transaction to the system-level MMU on behalf of the second MMU.

Continuity (3)
Continuation 16453995 · Jun 26, 2019
Continuation 15482690 · Apr 7, 2017
Related Publication 20210056051A1 · Feb 25, 2021
Cited By (1)
US 12,423,132