Technology to provide accurate training and per-bit deskew capability for high bandwidth memory input/output links
Systems, apparatuses and methods may provide for technology that programs a plurality of seed values into a plurality of linear feedback shift registers (LFSRs), wherein the plurality of LFSRs correspond to a data word (DWORD) and at least two of the plurality of seed values differ from one another. The technology may also train a link coupled to the plurality of LFSRs, wherein the plurality of seed values cause a parity bit associated with the DWORD to toggle while the link is being trained. In one example, the technology also automatically selects the plurality of seed values based on one or more of an expected traffic pattern on the link (e.g., after training) or a deskew constraint associated with the link.
1. A memory controller comprising:
one or more substrates; and
logic coupled to the one or more substrates, wherein the logic is at least partly implemented in one or more of configurable or fixed-functionality hardware, and the logic coupled to the one or more substrates is to:
program a plurality of seed values into a plurality of linear feedback shift registers (LFSRs), wherein the plurality of LFSRs correspond to a data word and at least two of the plurality of seed values differ from one another, and wherein each of the plurality of seed values differ from one another and are automatically selected to each differ from one another based on one or more of an expected traffic pattern on a link coupled to the plurality of LFSRs or a deskew constraint associated with the link; and
train the link coupled to the plurality of LFSRs.
2. The memory controller of claim 1 , wherein the plurality of seed values are to cause a parity bit associated with the data word to toggle while the link is being trained.
3. The memory controller of claim 1 , wherein to train the link, the logic coupled to the one or more substrates is to conduct a per-bit deskew on one or more lanes in the link.
4. The memory controller of claim 1 , wherein the plurality of LFSRs is to consist of an even number of LFSRs.
5. The memory controller of claim 1 , wherein the link is to be trained at a physical layer of a memory controller, and wherein the link is to be a high bandwidth memory link in a system on chip.
6. The memory controller of claim 1 , wherein to program the plurality of seed values into the plurality of LFSRs, the logic coupled to the one or more substrates is to:
program a first seed value into a first LFSR;
program a second seed value into a second LFSR;
program a third seed value into a third LFSR; and
program a fourth seed value into a fourth LFSR, wherein the first seed value, the second seed value, the third seed value, and the fourth seed value differ from one another.
7. A computing system comprising:
a memory controller including a plurality of linear feedback shift registers (LFSRs) corresponding to a data word;
a link coupled to the plurality of LFSRs;
a memory structure coupled to the memory controller, the memory structure including a set of instructions, which when executed by the memory controller, cause the memory controller to:
program a plurality of seed values into the plurality of LFSRs, wherein at least two of the plurality of seed values differ from one another, and wherein each of the plurality of seed values differ from one another and are automatically selected to each differ from one another based on one or more of an expected traffic pattern on a link coupled to the plurality of LFSRs or a deskew constraint associated with the link; and
train the link coupled to the plurality of LFSRs.
8. The computing system of claim 7 , wherein the plurality of seed values are to cause a parity bit associated with the data word to toggle while the link is being trained.
9. The computing system of claim 7 , wherein to train the link, the instructions, when executed, cause the memory controller to conduct a per-bit deskew on one or more lanes in the link.
10. The computing system of claim 7 , wherein the plurality of LFSRs consists of an even number of LFSRs.
11. The computing system of claim 7 , wherein the link is to be trained at a physical layer of the memory controller, wherein the computing system includes a system on chip (SoC), and wherein the link is a high bandwidth memory link in the SoC.
12. The computing system of claim 7 , wherein to program the plurality of seed values into the plurality of LFSRs, the instructions, when executed, cause the memory controller to:
program a first seed value into a first LFSR;
program a second seed value into a second LFSR;
program a third seed value into a third LFSR; and
program a fourth seed value into a fourth LFSR, wherein the first seed value, the second seed value, the third seed value, and the fourth seed value differ from one another.
13. At least one non-transitory computer readable storage medium comprising a set of instructions, which when executed by a computing system, cause the computing system to:
program a plurality of seed values into a plurality of linear feedback shift registers (LFSRs), wherein the plurality of LFSRs correspond to a data word and at least two of the plurality of seed values differ from one another, and wherein each of the plurality of seed values differ from one another and are automatically selected to each differ from one another based on one or more of an expected traffic pattern on a link coupled to the plurality of LFSRs or a deskew constraint associated with the link; and
train the link coupled to the plurality of LFSRs.
14. The at least one non-transitory computer readable storage medium of claim 13 , wherein the plurality of seed values are to cause a parity bit associated with the data word to toggle while the link is being trained.
15. The at least one non-transitory computer readable storage medium of claim 13 , wherein to train the link, the instructions, when executed, cause the computing system to conduct a per-bit deskew on one or more lanes in the link.
16. The at least one non-transitory computer readable storage medium of claim 13 , wherein the plurality of LFSRs is to consist of an even number of LFSRs.
17. The at least one non-transitory computer readable storage medium of claim 13 , wherein the link is to be trained at a physical layer of a memory controller, and wherein the link is to be a high bandwidth memory link in a system on chip.
18. The at least one non-transitory computer readable storage medium of claim 13 , wherein to program the plurality of seed values into the plurality of LFSRs, the instructions, when executed, cause the computing system to:
program a first seed value into a first LFSR;
program a second seed value into a second LFSR;
program a third seed value into a third LFSR; and
program a fourth seed value into a fourth LFSR, wherein the first seed value, the second seed value, the third seed value, and the fourth seed value differ from one another.
19. A method comprising:
programming a plurality of seed values into a plurality of linear feedback shift registers (LFSRs), wherein the plurality of LFSRs correspond to a data word and at least two of the plurality of seed values differ from one another, and wherein each of the plurality of seed values differ from one another and are automatically selected to each differ from one another based on one or more of an expected traffic pattern on a link coupled to the plurality of LFSRs or a deskew constraint associated with the link; and
training the link coupled to the plurality of LFSRs.
20. The method of claim 19 , wherein the plurality of seed values cause a parity bit associated with the data word to toggle while the link is being trained.