IP Library › Granted Patent US 11,373,966
Granted Patent B2
US 11,373,966 · App. 17/010,589 · Granted Jun 28, 2022

Embedded thin-film magnetic inductor design for integrated voltage regulator (IVR) applications

Inventors: Tae Hong Kim (Chandler, AZ); Jiangqi He (Chandler, AZ); Guotao Wang (Chandler, AZ)
Assignee: Huawei Technologies Co., Ltd.
H01L23/66H01L24/13H01L28/10H01L2223/6672H01L2924/1427
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Quick Facts
Patent No.
US 11,373,966
App. No.
17/010,589
Granted
Jun 28, 2022
Kind
B2
Abstract

A package including a package substrate; an interposer electrically coupled to the package substrate and including a metal layer; a die including an integrated voltage regulator and electrically coupled to the interposer by solder features; and an inductor formed by a magnetic material disposed between two of the solder features electrically coupled to each other by a portion of the metal layer of the interposer, the inductor electrically coupled to the integrated voltage regulator.

Claims (32)

1. A package, comprising:

a package substrate;

an interposer electrically coupled to the package substrate and including a metal layer;

a die including an integrated voltage regulator and electrically coupled to the interposer by solder features; and

an inductor formed by a magnetic material disposed between two of the solder features electrically coupled to each other by a portion of the metal layer of the interposer, wherein the inductor is electrically coupled to the integrated voltage regulator, and wherein a thickness of the magnetic material is limited to a height of the solder features.

2. The package of claim 1 , wherein the interposer comprises a passive silicon wafer.

3. The package of claim 1 , wherein the interposer comprises an active silicon wafer.

4. The package of claim 1 , wherein the solder features comprise microbumps.

5. The package of claim 1 , wherein the solder features comprise controlled collapse chip connection (C4) bumps.

6. The package of claim 1 , wherein an output of the integrated voltage regulator is electrically coupled to an input of the inductor.

7. The package of claim 1 , wherein an output of the inductor is electrically coupled to an input of a capacitor on the die.

8. The package of claim 7 , wherein an output of the capacitor on the die is electrically coupled to at least one electrical component on the die.

9. The package of claim 7 , wherein the inductor and the capacitor collectively form a filter configured to mitigate or eliminate a predetermined frequency of a direct current (DC) voltage output by the integrated voltage regulator.

10. The package of claim 9 , wherein the predetermined frequency corresponds to a switching speed of the integrated voltage regulator.

11. The package of claim 9 , wherein the predetermined frequency is in a range of about one hundred mega Hertz (MHz) to about one hundred and fifty MHz.

12. The package of claim 1 , wherein the inductor is configured to mitigate or prevent a ripple effect produced by the integrated voltage regulator.

13. The package of claim 1 , wherein an output of the integrated voltage regulator is electrically coupled to an input of the inductor, an output of the inductor is electrically coupled to an input of a capacitor on the die, and an output of the capacitor on the die is electrically coupled to at least one electrical component on the die.

14. A package, comprising:

a package substrate including a metal layer;

an interposer including an integrated voltage regulator and electrically coupled to the package substrate by solder features;

a die electrically coupled to the interposer; and

an inductor formed by a magnetic material disposed between and abutting against exterior surfaces of two of the solder features electrically coupled to each other by a portion of the metal layer of the package substrate, wherein the inductor is electrically coupled to the integrated voltage regulator.

15. The package of claim 14 , wherein a thickness of the magnetic material is limited to a height of the solder features.

16. The package of claim 14 , wherein the solder features comprise microbumps or controlled collapse chip connection (C4) bumps.

17. A package, comprising:

a printed circuit board including a metal layer;

a package substrate electrically coupled to the printed circuit board by solder features;

an interposer electrically coupled to the package substrate;

a die electrically coupled to the interposer, wherein one of the die, the interposer, and the package having an integrated voltage regulator embedded therein; and

an inductor formed by magnetic means disposed between two of the solder features electrically coupled to each other by a portion of the metal layer of the printed circuit board, wherein the inductor is electrically coupled to the integrated voltage regulator.

18. The package of claim 17 , wherein a thickness of the magnetic means is limited to a height of the solder features.

19. The package of claim 17 , wherein the solder features comprise microbumps or controlled collapse chip connection (C4) bumps.

Assignments (1)
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded May 5, 2022
From: FUTUREWEI TECHNOLOGIES, INC.
To: HUAWEI TECHNOLOGIES CO., LTD.
Reel/Frame 059832/0683 →
Continuity (3)
Continuation PCTCN2019110121 · Oct 9, 2019
Provisional Application 62751381 · Oct 26, 2018
Related Publication 20200402934A1 · Dec 24, 2020
Cited By (2)
US 12,289,898 US 12,628,358