Semiconductor device assemblies including multiple stacks of different semiconductor dies
A semiconductor device assembly is provided. The assembly comprises a package substrate, a first stack of semiconductor dies having a first set of planform dimensions disposed over a first location on the substrate, a second stack of semiconductor dies having a second set of planform dimensions different from the first set disposed over a second location on the substrate, and an encapsulant at least partially encapsulating the substrate, the first stack and the second stack. The first stack of semiconductor dies has a first planform area, the second stack of semiconductor dies has a second planform area, and a sum of the first and second planform areas can be at least 50%, 67%, 75%, or even more of an area of the package substrate.
1. A semiconductor device assembly, comprising:
a package substrate having an upper surface with an upper surface area;
a first shingled stack including a plurality of first semiconductor dies, each first semiconductor die of the plurality having a first length and a first width, the first shingled stack overlying a first area of the substrate with a first set of planform dimensions;
a second shingled stack including a plurality of second semiconductor dies, each second semiconductor die of the plurality having a second length and a second width, the second shingled stack overlying a second area of the substrate with a second set of planform dimensions different from the first set; and
an encapsulant at least partially encapsulating the substrate, the first shingled stack and the second shingled stack,
wherein the first length is different than the second length and the second width.
2. The semiconductor device assembly of claim 1 , wherein the first set of planform dimensions includes a first lateral dimension and a second lateral dimension, and wherein the second set of planform dimensions includes a third lateral dimension and a fourth lateral dimension, and wherein the lateral dimension is different than the third lateral dimension and the fourth lateral dimension.
3. The semiconductor device assembly of claim 2 , wherein the second lateral dimension is different than the third lateral dimension and the fourth lateral dimension.
4. The semiconductor device assembly of claim 1 , wherein a sum of the first area and the second area is at least 50% of the upper surface area of the package substrate.
5. The semiconductor device assembly of claim 4 , wherein the sum is at least 67% of the upper surface area of the package substrate.
6. The semiconductor device assembly of claim 4 , wherein the sum is at least 75% of the upper surface area of the package substrate.
7. The semiconductor device assembly of claim 4 , wherein the sum is at least 90% of the upper surface area of the package substrate.
8. The semiconductor device assembly of claim 1 , wherein the first shingled stack of semiconductor dies is connected to the package substrate by a first plurality of wirebonds and the second shingled stack of semiconductor dies is connected to the package substrate by a second plurality of wirebonds.
9. The semiconductor device assembly of claim 1 , wherein the first semiconductor dies of the first shingled stack are offset from one another in a first direction.
10. The semiconductor device assembly of claim 9 , wherein the second semiconductor dies of the second shingled stack are offset from one another in a second direction different from the first direction.
11. The semiconductor device assembly of claim 1 , wherein the first shingled stack of semiconductor dies comprises a first plurality of memory dies, and wherein the second shingled stack of semiconductor dies comprises a second plurality of memory dies.
12. The semiconductor device assembly of claim 11 , wherein the first plurality of memory dies and the second plurality of memory dies comprise a single memory type.
13. The semiconductor device assembly of claim 12 , wherein the single memory type is one of NAND flash, NOR flash, DRAM, PCM, FeRAM, or MRAM.
14. The semiconductor device assembly of claim 1 , wherein the package substrate includes a plurality of external connectors operably connected to the first and second shingled stacks of semiconductor dies.
15. The semiconductor device assembly of claim 1 , further comprising:
a third shingled stack including a plurality of third semiconductor dies, each third semiconductor die of the plurality having a third length and a third width, the third shingled stack overlying a third area of the substrate with a third set of planform dimensions different from the first set and the second set.
16. A method of making a memory device, comprising:
providing a substrate having an upper surface with an upper surface area;
stacking a plurality of first semiconductor dies in a first shingled stack, each first semiconductor die of the plurality having a first length and a first width, the first shingled stack overlying a first area of the substrate with a first set of planform dimensions;
stacking a plurality of second semiconductor dies in a second shingled stack, each second semiconductor die of the plurality having a second length and a second width, the second shingled stack overlying a second area of the substrate with a second set of planform dimensions different from the first set; and
providing an encapsulant to at least partially encapsulate the substrate, the first shingled stack and the second shingled stack,
wherein the first length is different than the second length and the second width.
17. The method of claim 16 , wherein the first set of planform dimensions includes a first lateral dimension and a second lateral dimension, and wherein the second set of planform dimensions includes a length third lateral dimension and a fourth lateral dimension, and wherein the lateral dimension is different than the third lateral dimension and the fourth lateral dimension.
18. The method of claim 17 , wherein the second lateral dimension is different than the third lateral dimension and the fourth lateral dimension.
19. The method of claim 16 , wherein a sum of the first area and the second area is at least 50% of the upper surface area of the package substrate.
20. The method of claim 16 , wherein the first shingled stack of semiconductor dies comprises a first plurality of memory dies, and wherein the second shingled stack of semiconductor dies comprises a second plurality of memory dies.
21. The method of claim 20 , wherein the first plurality of memory dies and the second plurality of memory dies comprise a single memory type.