Split-steer amplifier with invertible output
A split-steer amplifier with an invertible phase output, includes a first transistor having its base coupled to a positive node of an input port, its emitter coupled to ground, and collector connected to a positive intermediate node; a second transistor having its base coupled to a negative node of the input port, its emitter coupled to ground, and collector connected to a negative intermediate node; and multiple output ports each having a transistor arrangement operable to couple a positive node of that output port to the positive intermediate node and a negative node of that output port to the negative intermediate node, operable to couple the positive node of that output port to the negative intermediate node and the negative node of that output port to the positive intermediate node, and operable to decouple the positive node and the negative node of that output port from the intermediate nodes.
1. A split-steer amplifier with at least one output having an invertible phase, the amplifier comprising:
a first input transistor having its base coupled to a positive node of an input port, its emitter coupled to ground, and its collector connected to a positive intermediate node;
a second input transistor having its base coupled to a negative node of the input port, its emitter coupled to ground, and its collector connected to a negative intermediate node; and
multiple output ports each having a transistor arrangement that is configured to:
when enabled with a first polarity, couple a positive node of that output port to the positive intermediate node and couples a negative node of that output port to the negative intermediate node;
when enabled with a second polarity, couple the positive node of that output port to the negative intermediate node and couples the negative node of that output port to the positive intermediate node; and
when disabled, decouple the positive node and the negative node of that output port from each of the positive and negative intermediate nodes, wherein the bases of the first and second input transistors being biased to provide quiescent current m*I0 when m of the multiple output ports are enabled, and
wherein the enabling of the multiple output ports with the first polarity or the second polarity is associated with an orthogonal phase code that identifies a receive signal corresponding to a receive antenna or identifies a transmit signal corresponding to a transmit antenna.
2. The amplifier of claim 1 , wherein m equals two.
3. The amplifier of claim 1 , wherein the first input transistor is an NPN bipolar junction transistor and the second input transistor is an NPN bipolar junction transistor.
4. The amplifier of claim 1 , wherein the positive node of the input port is configured to a positive component of a differential signal and the negative node of the input port is configured to receive a negative component of the differential signal.
5. The amplifier of claim 4 , wherein the differential signal is an oscillation signal generated by a local oscillator.
6. The amplifier of claim 1 , wherein a first output port from among the multiple output ports is connected to a first mixer of a mixer pair and a second output port from among the multiple output ports is connected to second mixer of the mixer pair.
7. The amplifier of claim 1 , wherein each transistor arrangement comprises a first pair of transistors with their bases coupleable to a first voltage source operable to provide a first voltage and a second voltage, the second voltage being higher than the first voltage, and a second pair of transistors with their bases coupleable to a third voltage and a fourth voltage, the fourth voltage being higher than the third voltage.
8. The amplifier of claim 7 , wherein the transistors of the first pair of transistors are NPN bipolar junction transistors and the transistors of the second pair of transistors are NPN bipolar junction transistors.
9. The amplifier of claim 7 , wherein coupling the bases of the first pair of transistors to the first voltage and the bases of the second pair of transistors to the fourth voltage enables an output port from among the multiple output ports enables the output port with the first polarity.
10. The amplifier of claim 7 , wherein coupling the bases of the first pair of transistors to the second voltage and the bases of the second pair of transistors to the third voltage enables an output port from among the multiple output ports with second first polarity.
11. The amplifier of claim 7 , wherein:
coupling the bases of the first pair of transistors to the first voltage and the bases of the second pair of transistors to the fourth voltage enables an output port from among the multiple output ports enables the output port with the first polarity; and
coupling the bases of the first pair of transistors to the second voltage and the bases of the second pair of transistors to the third voltage enables an output port from among the multiple output ports with second polarity, the second polarity being 180 degrees opposite the first polarity.
12. The amplifier of claim 7 , wherein the first voltage and the third voltage are the same, and wherein the second voltage and the fourth voltage are the same.
13. The amplifier of claim 7 , further comprising a digital controller, wherein the digital controller is configured to alternatingly couple the bases of the first pair of transistors to the first voltage while coupling the bases of the second pair of transistors to the fourth voltage, or couple the bases of the first pair of transistors to the second voltage while coupling the bases of the second pair of transistors to the third voltage.
14. The amplifier of claim 13 , wherein the number of output ports is two, and wherein the digital controller is further configured to:
supply a first bias current to the first input transistor and the second input transistor when one output port is enabled and one output port is disabled; and
supply a second bias current to the first input transistor and the second input transistor when both output ports are enabled, the second bias current being greater than the first bias current.
15. The amplifier of claim 14 , wherein the digital controller is further configured to:
supply the second bias current by coupling the first input transistor and the second input transistor to a first current source and a second current source; and
supply the first bias current by coupling the first input transistor and the second input transistor to the first current source and decoupling the first input transistor and the second input transistor from the second current source.
16. The amplifier of claim 15 , wherein the first current source comprises a first P-channel MOSFET with its drain terminal connected to a collector and base or a drain terminal and gate terminal of a third transistor, and wherein the second current source comprises a second P-channel MOSFET with its drain terminal connected to the collector and base of the third transistor.
17. The amplifier of claim 16 , wherein the source terminal of the first P-channel MOSFET and source terminal of the second P-channel MOSFET are connected to a common supply voltage.
18. The amplifier of claim 17 , wherein the third transistor is an NPN bipolar junction transistor.
19. A method of operating an amplification circuit, the method comprising coupling a base of a first input transistor of the amplification circuit to a positive node of an input port, coupling an emitter of the first input transistor to ground, and coupling the collector of the first input transistor to a positive intermediate node;
coupling a base of a second input transistor of the amplification circuit to a negative node of the input port, coupling the emitter of the second transistor to ground, and coupling the collector of the second amplification circuit to a negative intermediate node;
enabling a selected one of multiple output ports with a first polarity by coupling a positive node of the selected output port to the positive intermediate node and coupling a negative node of the selected output port to the negative intermediate node;
inverting the polarity of the selected output port by coupling the positive node of the selected output port to the negative intermediate node and coupling the negative node of the selected output port to the positive intermediate node; and
when m of the multiple output ports are enabled, biasing the bases of the first and second input transistors to provide quiescent current m*I0, wherein the enabling of the multiple output ports with the first polarity or the inverted polarity is associated with an orthogonal phase code that identifies a receive signal corresponding to a receive antenna or identifies a transmit signal corresponding to a transmit antenna.
20. The method of claim 19 , further comprising enabling a second of the multiple output ports with the first polarity by coupling the positive node of the second output port to the positive intermediate node and coupling the negative node of the second output port to the negative intermediate node.