Electronic device for controlling command input

1. An electronic device comprising:

a command generation circuit configured to generate a refresh command and a driving control signal, which are enabled during an all-bank refresh operation, according to a logic level combination of an internal chip selection signal and an internal command address; and

a buffer control circuit configured to generate, from the refresh command and the driving control signal, a first buffer enable signal for enabling a first group of buffers and a second buffer enable signal for enabling a second group of buffers.

2. The electronic device of claim 1 , wherein during the all-bank refresh operation, the first group of buffers are disabled, and the second group of buffers are enabled.

3. The electronic device of claim 1 , wherein the internal command address comprises a first group of internal command addresses and a second group of internal command addresses, and

wherein the electronic device further comprises a buffer circuit configured to generate the internal chip selection signal and the first and second groups of internal command addresses from a chip selection signal, a first group of command addresses, and a second group of command addresses, through the first group of buffers and the second group of buffers which are enabled by the first buffer enable signal and the second buffer enable signal.

4. The electronic device of claim 3 , wherein the buffer circuit comprises:

a chip selection signal buffer circuit configured to generate the internal chip selection signal by buffering the chip selection signal in synchronization with an internal clock;

a first command buffer circuit comprising the first group of buffers, the first command buffer circuit configured to be enabled by the first buffer enable signal and generate the first group of internal command addresses from the first group of command addresses; and

a second command buffer circuit comprising the second group of buffers, the second command buffer circuit configured to be enabled by the second buffer enable signal and generate the second group of internal command addresses from the second group of command addresses.

5. The electronic device of claim 4 , wherein the first command buffer circuit comprises:

a first buffer configured to be enabled by the first buffer enable signal and generate a first input command address by buffering the first group of command addresses;

a first delay circuit configured to generate a first delayed command address by delaying the first input command address; and

a first transfer circuit configured to generate the first group of internal command addresses from the first delayed command address in synchronization with the internal clock.

6. The electronic device of claim 5 , wherein the first buffer is set to the first group of buffers.

7. The electronic device of claim 4 , wherein the second command buffer circuit comprises:

a second buffer configured to be enabled by the second buffer enable signal and generate a second input command address by buffering the second group of command addresses;

a second delay circuit configured to generate a second delayed command address by delaying the second input command address; and

a second transfer circuit configured to generate the second group of internal command addresses from the second delayed command address in synchronization with the internal clock.

8. The electronic device of claim 7 , wherein the second buffer is set to the second group of buffers.

9. The electronic device of claim 1 , wherein the command generation circuit comprises:

a command input circuit configured to generate an input command from the internal command address according to the driving control signal;

a command decoder configured to generate the refresh command and an internal command according to a logic level combination of the internal chip selection signal and the input command in synchronization with an internal clock; and

a driving control signal generation circuit configured to generate the driving control signal which is enabled in a predetermined period by an all-bank information signal and the refresh command which are inputted through the internal command address.

10. The electronic device of claim 1 , wherein the buffer control circuit comprises:

a pre-enable signal generation circuit configured to generate a pre-enable signal which is enabled from a point of time that the refresh command is inputted to a point of time that the internal chip selection signal is inputted; and

a logic circuit configured to generate the first buffer enable signal by inverting and buffering the pre-enable signal, and generate the second buffer enable signal by inverting and buffering the pre-enable signal during a period in which the driving control signal is enabled.

11. An electronic device comprising:

a command generation circuit configured to generate a refresh command and a driving control signal, which are enabled during an all-bank refresh operation, according to a logic level combination of an internal chip selection signal, a first group of internal command addresses, and a second group of internal command addresses, and configured to generate an internal command by detecting a logic level combination of the internal chip selection signal and the second group of internal command addresses during the all-bank refresh operation; and

a buffer control circuit configured to generate, from the refresh command and the driving control signal, a first buffer enable signal for enabling a first group of buffers and a second buffer enable signal for enabling a second group of buffers.

12. The electronic device of claim 11 , wherein the internal command is generated from the internal chip selection signal and the second group of internal command addresses which are inputted through the second group of buffers.

13. The electronic device of claim 11 , wherein during the all-bank refresh operation, the first group of buffers are disabled, and the second group of buffers are enabled.

14. The electronic device of claim 11 , wherein the first group of buffers are enabled to generate the first group of internal command addresses when the first buffer enable signal is enabled, and disabled to block the generation of the first group of internal command addresses when the first buffer enable signal is disabled, and

the second group of buffers are enabled to generate the second group of internal command addresses when the second buffer enable signal is enabled, and disabled to block the generation of the first group of internal command addresses when the second buffer enable signal is disabled.

15. The electronic device of claim 11 , wherein the command generation circuit comprises:

a command input circuit configured to generate an input command from the first and second groups of internal command addresses according to the driving control signal;

a command decoder configured to generate the refresh command and the internal command according to a logic level combination of the internal chip selection signal and the input command in synchronization with an internal clock; and

a driving control signal generation circuit configured to generate the driving control signal which is enabled in a predetermined period by an all-bank information signal and the refresh command which are inputted through the first and second groups of internal command addresses.

16. The electronic device of claim 15 , wherein the command input circuit blocks the input of the first group of internal command addresses, when the driving control signal is enabled.

17. The electronic device of claim 15 , wherein the command decoder comprises:

a pre-decoder configured to generate a pre-refresh command and a pre-internal command by decoding the input command address; and

a synchronization circuit configured to generate the refresh command and the internal command from the pre-refresh command and the pre-internal command when the internal chip selection signal is inputted in synchronization with the internal clock.

18. The electronic device of claim 17 , wherein the synchronization circuit comprises:

a first synchronization circuit configured to generate the refresh command from the pre-refresh command when the internal chip selection signal is inputted in synchronization with the internal clock; and

a second synchronization circuit configured to generate the internal command from the pre-internal command when the internal chip selection signal is inputted in synchronization with the internal clock.

19. The electronic device of claim 15 , wherein the driving control signal generation circuit comprises:

an all-bank refresh signal generation circuit configured to generate an all-bank refresh signal from the all-bank information signal during a period in which the refresh command is inputted; and

a latch circuit configured to generate the driving control signal which is enabled by the all-bank refresh signal and disabled after a predetermined period.

20. The electronic device of claim 11 , wherein the buffer control circuit comprises:

a pre-enable signal generation circuit configured to generate a pre-enable signal which is enabled from a point of time that the refresh command is inputted to a point of time that the internal chip selection signal is inputted; and

a logic circuit configured to generate the first buffer enable signal by inverting and buffering the pre-enable signal, and configured to generate the second buffer enable signal by inverting and buffering the pre-enable signal during a period in which the driving control signal is enabled.