System and method for obfuscation of electronic circuits
View Patent ↗A computer-implemented method of generating randomized electrical interconnects for an electronic circuit comprises steps of receiving a netlist of nodes of electronic components to be connected, each connection between the nodes forming an electrical interconnect; determining a list of one or more path directions for each electrical interconnect; determining a plurality of path direction distances for each electrical interconnect; generating a plurality of segments for each electrical interconnect, each segment having one path direction and a length which are selected at random; calculating a sum of the lengths of all segments of the plurality of segments in each path direction each time a segment is generated for each electrical interconnect; removing one path direction from the list of path directions when a first condition is met; and stopping the generating a plurality of segments for each electrical interconnect when a second condition is met.
1. A computing device for generating randomized electrical interconnects for an electronic circuit, the computing device comprising:
a processing element in electronic communication with a memory element, the processing element configured or programmed to:
create a three-dimensional grid that fits a space of a printed circuit board,
receive a netlist of nodes of electronic components of the electronic circuit to be connected, each connection of nodes forming an electrical interconnect with a start node and an end node,
determine a list of one or more path directions for each electrical interconnect,
determine a plurality of path direction distances for each electrical interconnect,
generate a plurality of segments for each electrical interconnect, each segment of the plurality of segments having one path direction and a length which are selected at random,
calculate a sum of the lengths of all segments of the plurality of segments in each path direction each time a segment of the plurality of segments is generated for each electrical interconnect,
remove one path direction from the list of one or more path directions when the sum of the lengths of the all segments of the plurality of segments in the one path direction is equal to the path direction distance determined for each electrical interconnect, and
stop generating a plurality of segments for each electrical interconnect when a sum of the lengths of all segments of the plurality of segments in each path direction is equal to each path direction distance for each electrical interconnect.
2. The computing device of claim 1 , wherein, for each electrical interconnect, the list of one or more path directions are selected from −X, +X, −Y, +Y, −Z, and +Z.
3. The computing device of claim 1 , wherein, for each electrical interconnect, the list of one or more path directions are determined by subtracting a value at each dimension coordinate of the start node from a value at each dimension coordinate of the end node and keeping sign of a value of a result of the subtracting in each dimension coordinate.
4. The computing device of claim 1 , wherein, for each electrical interconnect, each path direction distance of the plurality of path direction distances is determined by subtracting a value at each dimension coordinate of the start node from a value at each dimension coordinate of the end node and taking an absolute value of each dimension coordinate.
5. The computing device of claim 1 , wherein, for each electrical interconnect, a first segment starts at the start node, each subsequent segment starts at an end of an immediately previous segment, and a last segment ends at the end node.
6. A computing device for generating randomized electrical interconnects for an electronic circuit, the computing device comprising:
a processing element in electronic communication with a memory element, the processing element configured or programmed to:
create a three-dimensional grid that fits a space of a printed circuit board,
receive a netlist of nodes of electronic components of the electronic circuit to be connected, each connection of nodes forming an electrical interconnect with a start node and an end node,
choose an initial Z-value for the start node at random for each electrical interconnect,
determine a list of one or more path directions for each electrical interconnect,
determine a plurality of path direction distances for each electrical interconnect,
generate a plurality of segments for each electrical interconnect, each segment of the plurality of segments having one path direction and a length which are selected at random,
calculate a sum of the lengths of all segments of the plurality of segments in each path direction each time a segment of the plurality of segments is generated for each electrical interconnect,
remove one path direction from the list of one or more path directions when the sum of the lengths of the all segments of the plurality of segments in the one path direction is equal to the path direction distance determined for each electrical interconnect, and
stop generating a plurality of segments for each electrical interconnect when a sum of the lengths of all segments of the plurality of segments in each path direction is equal to each path direction distance for each electrical interconnect.
7. The computing device of claim 6 , wherein the electronic circuit includes a maximum number of electrically conductive layers and, for each electrical interconnect, the initial Z-value is selected from a range of 1 to the maximum number of electrically conductive layers −1.
8. The computing device of claim 6 , wherein, for each electrical interconnect, the list of one or more path directions are selected from −X, +X, −Y, and +Y.
9. The computing device of claim 6 , wherein, for each electrical interconnect, the list of one or more path directions are determined by subtracting X and Y values of the start node from X and Y values of the end node and keeping sign of a difference of said subtracting.
10. The computing device of claim 6 , wherein, for each electrical interconnect, X and Y path direction distances are determined by subtracting X and Y values of the start node from X and Y values of the end node and taking an absolute value of a difference of said subtracting.
11. The computing device of claim 6 , wherein, for each electrical interconnect, a first segment starts at the start node, each subsequent segment starts at an end of a segment immediately previous to said each subsequent segment, and a last segment ends at the end node.
12. A computing device for generating randomized electrical interconnects for an electronic circuit, the computing device comprising:
a processing element in electronic communication with a memory element, the processing element configured or programmed to perform steps of:
receiving a netlist of nodes of electronic components to be connected, each connection between the nodes of the netlist of nodes forming an electrical interconnect with a start node and an end node;
selecting a geometric shape or a mathematical function at random to determine a path for each electrical interconnect; and
selecting an interconnect length at random for each electrical interconnect.
13. The computing device of claim 12 , further comprising a step of adding a noise to the geometric shape or the mathematical function of each electrical interconnect.
14. The computing device of claim 13 , wherein the noise includes an additive white Gaussian noise.
15. The computing device of claim 12 , wherein the geometric shape includes a plurality of connected segments such that a first segment starts at the start node of the first segment, each subsequent segment starts at an end of a previous segment, and a last segment ends at the end node of the last segment.
16. The computing device of claim 15 , wherein the plurality of segments do not align with orthogonal X, Y, and Z axes.
17. The computing device of claim 12 , wherein the geometric shape includes a single segment with a curvature or rounded shape.
18. The computing device of claim 12 , wherein the interconnect length of said each electrical interconnect is selected at random from a range that is greater than a minimum value determined by a distance between the start node and the end node of said each electrical interconnect and that is less than or equal to a maximum value determined by a maximum propagation delay for said each electrical interconnect.