Integrated standard cell structure

1. An integrated circuit, comprising:

a first standard cell having a first p-type field-effect transistor (pFET) and a first n-type field-effect transistor (nFET) integrated, and having a first dielectric gate on a first standard cell boundary;

a second standard cell being adjacent to the first standard cell, having a second pFET and a second nFET integrated, and having a second dielectric gate on a second standard cell boundary; and

a first filler cell configured between the first and second standard cells, and spanning between the dielectric gate and the second dielectric gate, wherein

the first pFET and the second pFET are formed on a first continuous active region,

the first nFET and the second nFET are formed on a second continuous active region, and

the first filler cell includes a third dielectric gate between the first and second dielectric gates and equally distanced away from the first and second dielectric gates.

2. The integrated circuit of claim 1 , further comprising:

a fourth dielectric gate and a fifth dielectric gate, wherein

the first standard cell spans between the first dielectric gate and the fourth dielectric gate along a first direction, and

the second standard cell spans between the second dielectric gate and the fifth dielectric gate along the first direction.

3. The integrated circuit of claim 2 , wherein

each of the first continuous active region and the second continuous active region extends through the first standard cell, the first filler cell, and the second standard cell, and

each of the first, second, third, fourth and fifth dielectric gates extends from the first continuous active region to the second continuous active region along a second direction that is orthogonal to the first direction.

4. The integrated circuit of claim 3 , wherein

the first filler cell spans a one-pitch dimension P from the first dielectric gate to the second dielectric gate along the first direction;

the first standard cell spans a first dimension D 1 from the fourth dielectric gate to the first dielectric gate along the first direction; and

the second standard cell spans a second dimension D 2 from the second dielectric gate to the fifth dielectric gate along the first direction, wherein D 2 =D 1 =P.

5. The integrated circuit of claim 3 , wherein

the first standard cell further includes a first gate stack extending from the first continuous active region to the second continuous active region along the second direction; and

the second standard cell further includes a second gate stack extending from the first continuous active region to the second continuous active region along the second direction.

6. The integrated circuit of claim 5 , wherein

the first gate stack is interposed between the first dielectric gate and the fourth dielectric gate, and is equally distanced from the first and fourth dielectric gates; and

the second gate stack is interposed between the second dielectric gate and the fifth dielectric gate, and is equally distanced from the second and fifth dielectric gates.

7. The integrated circuit of claim 6 , wherein

the first gate stack is equally distanced from the first and fourth dielectric gates; and

the second gate stack is equally distanced from the second and fifth dielectric gates.

8. The integrated circuit of claim 5 , wherein

the first standard cell further includes a third gate stack directly on the first continuous active region and a sixth dielectric gate on the second continuous active region, wherein the third gate stack extends along the second direction to contact the sixth dielectric gate; and

the second standard cell further includes a seventh dielectric gate on the first continuous active region and a fourth gate stack directly on the second continuous active region, wherein the seventh dielectric gate extends along the second direction to contact the fourth gate stack.

9. The integrated circuit of claim 5 , wherein

the first standard cell further includes a third gate stack directly on the first continuous active region and a sixth dielectric gate on the second continuous active region, wherein the third gate stack extends along the second direction to contact the sixth dielectric gate; and

the second standard cell further includes a seventh dielectric gate on the second continuous active region and a fourth gate stack directly on the first continuous active region, wherein the seventh dielectric gate extends along the second direction to contact the fourth gate stack.

10. The integrated circuit of claim 2 , further comprising

a third standard cell having a third pFET and a third nFET integrated, and having a sixth dielectric gate on a third standard cell boundary; and

a second filler cell configured between the second and third standard cells, wherein

the second filler cell spans from the fifth dielectric gate to the sixth dielectric gate,

the third pFET is formed on the first continuous active region,

the third nFET is formed on the second continuous active region, and

the third standard cell adjoins the second filler cell on the sixth dielectric gate.

11. An integrated circuit, comprising:

a first standard cell having a first gate stack, a first dielectric gate on a first standard cell boundary, and a second dielectric gate;

a second standard cell having a second gate stack, a third dielectric gate on a second standard cell boundary, and a fourth dielectric gate;

a first filler cell disposed between the first and second standard cells, and spanning from the first dielectric gate and the third dielectric gate;

a first continuous active region extending through the first standard cell, the first filler cell and the second standard cell; and

a second continuous active region extending through the first standard cell, the first filler cell and the second standard cell, wherein

each of the first gate stack, the second gate stack, the first dielectric gate, the second dielectric gate, the third dielectric gate and the fourth dielectric gate is extending from the first continuous active region to the second continuous active region along a first direction, and

each of the first and second standard cells and the first filler cell spans a same dimension along a second direction being perpendicular to the first direction.

12. The integrated circuit of claim 11 , wherein the first filler cell spans a one-pitch dimension P from the first dielectric gate and the third dielectric gate along the second direction, wherein the first standard cell spans a first dimension D 1 from the first dielectric gate to the second dielectric gate along the second direction; and

the second standard cell spans a second dimension D 2 from the third dielectric gate to the fourth dielectric gate along the second direction, wherein D 2 =D 1 =P.

13. The integrated circuit of claim 11 , wherein

the first standard cell further includes a third gate stack and a fifth dielectric gate being aligned along the first direction and contacted each other; and

the second standard cell further includes a fourth gate stack and a sixth dielectric gate being aligned along the first direction and contacted each other.

14. The integrated circuit of claim 13 , wherein

the third gate stack and the fifth dielectric gate contact each other; and

the fourth gate stack and the sixth dielectric gate contact each other.

15. The integrated circuit of claim 13 , wherein

the third gate stack and the sixth dielectric gate are formed directly on the first continuous active region; and

the fifth dielectric gate and the fourth gate stack are formed directly on the second continuous active region.

16. The integrated circuit of claim 13 , wherein

the third gate stack and the fourth gate stack are formed directly on the first continuous active region; and

the fifth dielectric gate and the sixth dielectric gate are formed directly on the second continuous active region.

17. The integrated circuit of claim 11 , wherein

the first standard cell includes a first p-type field-effect transistor (pFET) associated with the first gate stack and formed on the first continuous active region, and a first n-type field-effect transistor (nFET) associated with the first gate stack and formed on the second continuous active region; and

the second standard cell includes a second pFET associated with the second gate stack and formed on the first continuous active region, and a second nFET integrated associated with the second gate stack and formed on the second continuous active.

18. An integrated circuit, comprising:

a first standard cell having a first gate stack, a second gate stack, a first dielectric gate on a first standard cell boundary and a second dielectric gate contacting the second gate stack;

a second standard cell having a third gate stack, a fourth gate stack, a third dielectric gate on a second standard cell boundary, and a fourth dielectric gate contacting the fourth gate stack;

a first filler cell disposed between the first and second standard cells, and spanning from a fifth dielectric gate to a sixth dielectric gate, the first filler cell further including a seventh dielectric gate equally distanced from the fifth and sixth dielectric gates;

a first continuous active region extending through the first standard cell, the first filler cell and the second standard cell; and

a second continuous active region extending through the first standard cell, the first filler cell and the second standard cell, wherein

the first filler cell adjoins the first standard cell on the fifth dielectric gate and adjoins the second standard cell on the sixth dielectric gate; and

each of the first and second gate stacks and each of the first, third, fifth, sixth and seventh dielectric gates are extending from the first continuous active region to the second continuous active region.

19. The integrated circuit of claim 18 , wherein

the first and second continuous active regions extend from the first dielectric gate to the third dielectric gate along a first direction; and

each of the first and second standard cells and the first filler cell spans a same dimension along a second direction being perpendicular to the first direction.

20. The integrated circuit of claim 19 , wherein

the first filler cell spans a two-pitch dimension 2*P from the fifth dielectric gate and the sixth dielectric gate along the first direction;

the first standard cell spans a first dimension D 1 from the first dielectric gate to the fifth dielectric gate along the first direction; and

the second standard cell spans a second dimension D 2 from the third dielectric gate to the sixth dielectric gate along the first direction, wherein D 2 =D 1 =3*P.