IP Library Granted Patent US 11,900,156
Granted Patent B2
US 11,900,156 · App. 17/015,275 · Granted Feb 13, 2024

Inter-thread communication in multi-threaded reconfigurable coarse-grain arrays

Inventors: Yoav Etsion (Atlit, IL); Dani Voitsechov (Atlit, IL)
Assignee: SPEEDATA LTD.
G06F9/4881G06F9/3822G06F9/3836G06F9/3887G06F9/3889G06F9/5027G06F9/544
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Quick Facts
Patent No.
US 11,900,156
App. No.
17/015,275
Granted
Feb 13, 2024
Kind
B2
Abstract

A processor includes a compute fabric and a controller. The compute fabric includes an array of compute nodes and interconnects that configurably connect the compute nodes. The controller is configured to configure at least some of the compute nodes and interconnects in the compute fabric to execute specified code instructions, and to send to the compute fabric multiple threads that each executes the specified code instructions. A compute node among the compute nodes is configured to execute a code instruction for a first thread, and to transfer a result of the code instruction within the fabric, for use as an operand by a second thread, different from the first thread.

Claims (30)

1. A processor, comprising:

a compute fabric, which is configured to execute specified code instructions on different data in parallel using multiple threads, each thread executing the specified code instructions on respective different data, the compute fabric comprising an array of compute nodes and interconnects that configurably connect the compute nodes; and

a controller, configured to configure at least a group of the compute nodes in the array and at least some of the interconnects in the compute fabric to execute the specified code instructions, and instruct the compute fabric to execute the multiple threads,

wherein each compute node in the group is assigned by the controller to execute a respective same code instruction for the multiple threads,

wherein each compute node in the group comprises a respective token buffer for storing tokens, each token specifying (i) a respective operand on which the compute node is to execute the code instruction assigned to the compute node, and (ii) an identity of a thread that is to use the operand, wherein the token buffer comprises multiple slots for buffering the tokens, wherein each slot (a) is assigned to a respective thread, (b) has a slot identifier derived from an identifier of the thread, and (c) is configured to store metadata of the thread,

wherein a given compute node in the group is assigned to execute a given code instruction for the multiple threads,

and wherein another compute node in the group is configured to transfer an execution result from a first thread to a second thread, different from the first thread, by storing the execution result in the token buffer of the given compute node as a token that (i) specifies the execution result as the operand for the given code instruction, and (ii) specifies the second thread as the identity of the thread that is to use the operand.

2. The processor according to claim 1 , wherein the token buffer of the given compute node is formed from two or more token buffers of two or more of the compute nodes.

3. The processor according to claim 1 , wherein the another compute node is configured to assign the execution result to the second thread by saving the execution result to a slot assigned to the second thread.

4. The processor according to claim 1 , wherein the another compute node is configured to assign the result to the second thread by transferring to the token buffer of the given compute node, in addition to the execution result, metadata that specifies the identity of the second thread.

5. The processor according to claim 1 , wherein the multiple threads have a predefined order of execution, and wherein the first thread is earlier than the second thread in the order of execution.

6. The processor according to claim 1 , wherein the multiple threads have a predefined order of execution, and wherein the first thread is later than the second thread in the order of execution.

7. The processor according to claim 1 , wherein, in instructing the compute fabric to execute the multiple threads, the controller is configured to provide to the compute fabric a range of identifiers of the threads to be executed, and wherein the another compute node is configured to transfer the execution result only when an identifier of the second thread is within the range.

8. The processor according to claim 1 , wherein, in instructing the compute fabric to execute the multiple threads, the controller is configured to provide to the compute fabric a range of identifiers of the threads to be executed, and wherein the given compute node, which is assigned to use the execution result as an operand, is configured to use the transferred execution result only when an identifier of the second thread is within the range.

9. The processor according to claim 8 , wherein, when the identifier of the second thread is outside the range, the given compute node, which is assigned to use the execution result as an operand, is configured to obtain the operand for execution of the second thread from an alternative source.

10. The processor according to claim 1 , wherein the given compute node is further configured to transfer a result from a third thread to a fourth thread, different from the third thread, by storing the result in the token buffer of the given compute node.

11. A method, comprising:

in a processor that includes a compute fabric comprising an array of compute nodes and interconnects that configurably connect the compute nodes, the compute fabric being configurable to execute specified code instructions on different data in parallel using multiple threads, each thread executing the specified code instructions on respective different data, configuring at least a group of the compute nodes in the array and at least some of the interconnects in the compute fabric to execute the specified code instructions, including assigning each compute node in the group to execute a respective same code instruction for the multiple threads, and instructing the compute fabric to execute the multiple threads;

in each compute node in the group, maintaining a respective token buffer for storing tokens, each token specifying (i) a respective operand on which the compute node is to execute the code instruction assigned to the compute node, and (ii) an identity of a thread that is to use the operand, wherein the token buffer comprises multiple slots for buffering the tokens, wherein each slot (a) is assigned to a respective thread, (b) has a slot identifier derived from an identifier of the thread, and (c) is configured to store metadata of the thread;

assigning a given compute node in the group to execute a given code instruction for the multiple threads; and

in another compute node in the group, transferring an execution result from a first thread to a second thread, different from the first thread, by storing the execution result in the token buffer of the given compute node as a token that (i) specifies the execution result as the operand, and (ii) specifies the second thread as the identity of the thread that is to use the operand.

12. The method according to claim 11 , wherein the token buffer of the given compute node is formed from two or more token buffers of two or more of the compute nodes.

13. The method according to claim 11 , wherein transferring the execution result comprises assigning the execution result to the second thread by saving the result to a slot assigned to the second thread.

14. The method according to claim 11 , wherein assigning the execution result to the second thread comprises transferring to the token buffer of the given compute node, in addition to the execution result, metadata that specifies the identity of the second thread.

15. The method according to claim 11 , wherein the multiple threads have a predefined order of execution, and wherein the first thread is earlier than the second thread in the order of execution.

16. The method according to claim 11 , wherein the multiple threads have a predefined order of execution, and wherein the first thread is later than the second thread in the order of execution.

17. The method according to claim 11 , wherein instructing the compute fabric to execute the multiple threads comprises providing to the compute fabric a range of identifiers of the threads to be executed, and wherein transferring the execution result is performed only when an identifier of the second thread is within the range.

18. The method according to claim 11 , wherein instructing the compute fabric to execute the multiple threads comprises providing to the compute fabric a range of identifiers of the threads to be executed, and comprising, in the given compute node, which is assigned to use the execution result as an operand, using the transferred execution result only when an identifier of the second thread is within the range.

19. The method according to claim 18 , and comprising, when the identifier of the second thread is outside the range, obtaining the operand for execution of the second thread from an alternative source.

20. The method according to claim 11 , further comprising, in the given compute node, transferring a result from a third thread to a fourth thread, different from the third thread, by storing the result in the token buffer of the given compute node.

Assignments (3)
RELEASE OF SECURITY INTEREST Recorded Jul 3, 2025
From: KREOS CAPITAL VII AGGREGATOR SCSP
To: SPEEDATA LTD
Reel/Frame 071599/0362 →
SECURITY INTEREST Recorded Jul 11, 2023
From: SPEEDATA LTD
To: KREOS CAPITAL VII AGGREGATOR SCSP
Reel/Frame 064205/0454 →
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Sep 10, 2020
From: ETSION, YOAV; VOITSECHOV, DANI
To: SPEEDATA LTD.
Reel/Frame 053729/0749 →
Continuity (2)
Provisional Application 62904706 · Sep 24, 2019
Related Publication 20210089349A1 · Mar 25, 2021
Cited By (1)
US 12,608,225