Methods of erasing data in nonvolatile memory devices and nonvolatile memory devices performing the same
A nonvolatile memory device includes a memory cell region, a peripheral circuit region, a memory block in the memory cell region, and a control circuit in the peripheral circuit region. The memory cell region includes a first metal pad. The peripheral circuit region includes a second metal pad and is vertically connected to the memory cell region by the first metal pad and the second metal pad. The memory block includes a plurality of memory cells disposed in a vertical direction. The control circuit applies an erase voltage to an erase source terminal of the memory block, and applies a first voltage to a first selection line among a plurality of selection lines in the memory block. The first voltage is higher than the erase voltage. The first selection line is disposed closest to the erase source terminal among the plurality of selection lines and is used for selecting the memory block as an erase target block.
1. A nonvolatile memory device comprising:
a memory cell region including a first metal pad;
a peripheral circuit region including a second metal pad and vertically connected to the memory cell region by the first metal pad and the second metal pad;
a memory block in the memory cell region including a plurality of memory cells disposed in a vertical direction; and
a control circuit in the peripheral circuit region configured to apply an erase voltage to an erase source terminal of the memory block, and configured to apply a first voltage to a first selection line among a plurality of selection lines in the memory block, the first voltage being higher than the erase voltage, the first selection line being disposed closest to the erase source terminal among the plurality of selection lines and being used for selecting the memory block as an erase target block.
2. The nonvolatile memory device of claim 1 , wherein:
the control circuit is configured to apply a second voltage to a second selection line among the plurality of selection lines,
the second voltage is lower than the erase voltage, and
the second selection line is disposed farther from the erase source terminal than the first selection line and is used for selecting the memory block as the erase target block.
3. The nonvolatile memory device of claim 2 , wherein:
the first voltage starts to apply to the first selection line at a first time point, and
the erase voltage starts to apply to the erase source terminal at a second time point later than the first time point.
4. The nonvolatile memory device of claim 3 , wherein the second voltage starts to apply to the second selection line at a third time point later than the second time point.
5. The nonvolatile memory device of claim 2 , wherein the erase source terminal includes a common source line contact that is disposed in a lower portion of the memory block.
6. The nonvolatile memory device of claim 5 , wherein the control circuit is configured to apply the first voltage to a first ground selection line that is a lowermost ground selection line among at least two ground selection lines in the memory block.
7. The nonvolatile memory device of claim 6 , wherein the control circuit is configured to apply the second voltage to a second ground selection line that is disposed upper than the first ground selection line.
8. The nonvolatile memory device of claim 2 , wherein the erase source terminal includes a bitline that is disposed in an upper portion of the memory block.
9. The nonvolatile memory device of claim 8 , wherein the control circuit is configured to apply the first voltage to a first string selection line that is an uppermost string selection line among at least two string selection lines in the memory block.
10. The nonvolatile memory device of claim 9 , wherein the control circuit is configured to apply the second voltage to a second string selection line that is disposed lower than the first string selection line.
11. The nonvolatile memory device of claim 1 , wherein the first metal pad and the second metal pad are formed of copper.
12. The nonvolatile memory device of claim 1 , wherein the first metal pad and the second metal pad are connected by bonding manner.
13. The nonvolatile memory device of claim 1 , wherein the memory cell region is formed on a first wafer and the peripheral circuit region is formed on a second wafer.