IP Library › Granted Patent US 11,462,659
Granted Patent B2
US 11,462,659 · App. 17/015,732 · Granted Oct 4, 2022

Semiconductor light emitting device and manufacturing method of semiconductor light emitting device

Inventors: Satoshi Kamiyama (Nagoya, JP); Tetsuya Takeuchi (Nagoya, JP); Motoaki Iwaya (Nagoya, JP); Isamu Akasaki (Nagoya, JP); Lu Weifang (Nagoya, JP); Naoki Sone (Shizuoka, JP); Kazuyoshi Iida (Kiyosu, JP); Ryo Nakamura (Kiyosu, JP); Masaki Oya (Kiyosu, JP)
Assignees: KOITO MANUFACTURING CO., LTD.; MEIJO UNIVERSITY; TOYODA GOSEI CO., LTD.
H01L33/0093H01L33/0008H01L33/04H01L33/20H01L33/56
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Quick Facts
Patent No.
US 11,462,659
App. No.
17/015,732
Granted
Oct 4, 2022
Kind
B2
Abstract

Provided is a semiconductor light emitting device including a growth substrate; a pillar-shaped semiconductor layer formed on the growth substrate; and a buried semiconductor layer formed to cover the pillar-shaped semiconductor layer, wherein the pillar-shaped semiconductor layer has an n-type nanowire layer formed at a center, an active layer formed on an outermore side than the n-type nanowire layer, a p-type semiconductor layer formed on an outermore side than the active layer and a tunnel junction layer formed on an outermore side than the p-type semiconductor layer, and wherein at least a part of the pillar-shaped semiconductor layer is provided with a removed region formed by removing from the buried semiconductor layer to a part of the tunnel junction layer.

Claims (49)

1. A semiconductor light emitting device comprising:

a growth substrate;

a pillar-shaped semiconductor layer formed on the growth substrate; and

a buried semiconductor layer formed to cover the pillar-shaped semiconductor layer,

wherein the pillar-shaped semiconductor layer has an n-type nanowire layer formed at a center, an active layer formed on an outermore side than the n-type nanowire layer, a p-type semiconductor layer formed on an outermore side than the active layer and a tunnel junction layer formed on an outermore side than the p-type semiconductor layer, and

wherein at least a part of the pillar-shaped semiconductor layer is provided with a removed. region formed by removing from the buried semiconductor layer to apart of the tunnel junction layer.

2. The semiconductor light emitting device according to claim 1 , wherein a plurality of the pillar-shaped semiconductor layers is provided, and the removed region is provided over the plurality of pillar-shaped semiconductor layers.

3. The semiconductor light emitting device according to claim 1 , wherein the removed region is removed to a part of the p-type semiconductor layer.

4. The semiconductor light emitting device according to claim 1 , wherein the removed region is removed to a part of the active layer.

5. The semiconductor light emitting device according to claim 1 , wherein the removed region is removed to a part of the n-type nanowire layer.

6. The semiconductor light emitting device according to claim 1 , wherein an insulating film is formed on the removed region, and a transparent electrode is formed covering at least a part of the buried semiconductor layer and the removed region.

7. The semiconductor light emitting device according to claim 1 , wherein a high-resistance layer is formed on a top part of the n-type nanowire layer.

8. A growth method of a semiconductor light emitting device, the growth method comprising:

a mask process of forming a mask layer having an opening portion on a growth substrate;

a growth process of forming a pillar-shaped semiconductor layer in the opening portion by using selective growth; and

a burying process of growing a buried semiconductor layer on the growth substrate so as to cover the pillar-shaped semiconductor layer,

wherein the growth process comprises a process of forming an n-type nanowire layer, a process of forming an active layer on an outermore side than the n-type nanowire layer, a process of forming a p-type semiconductor layer on an outermore side than the active layer, and a process of forming a tunnel junction layer on an outermore side than the p-type semiconductor layer, and

wherein the growth method comprises:

a removing process of forming at least a part of the pillar-shaped semiconductor layer with a removed region by removing from the buried semiconductor layer to a part of the tunnel junction layer, after the burying process, and

an activation process of annealing the p-type semiconductor layer after the removing process.

9. A semiconductor light emitting device comprising:

a growth substrate; and

a pillar-shaped semiconductor layer formed on the growth substrate,

wherein the pillar-shaped semiconductor layer has an n-type nanowire layer formed at a center, an active layer formed on an outermore side than the n-type nanowire layer, and a p-type semiconductor layer formed on an outermore side than the active layer, and

wherein an inner surface protection layer made of a nitride semiconductor material containing Al is provided on a further n-side than the active layer.

10. The semicmductor light emitting device according to claim 9 , wherein the inner surface protection layer is provided covering an outer periphery of the n-type nanowire layer and in contact with the active laver.

11. The semiconductor light emitting device according to claim 9 , wherein at least Al is contained in the inner surface protection layer, and a maximum composition ratio of Al is 0.06 mol % or less.

12. The semiconductor light emitting device according to claim 9 , wherein a film thickness of the inner surface protection layer is equal to or greater than 1 nm and equal to or smaller than 100 nm.

13. A semiconductor light emitting device comprising:

a growth substrate; and

a pillar-shaped semiconductor layer formed on the growth substrate,

wherein the pillar-shaped semiconductor layer has an n-type nanowire layer formed at a center, an active layer fonned on an outermore side than the n-type nanowire layer, and a p-type semiconductor layer formed on an outermore side than the active layer, and

wherein an outer surface protection layer made of a nitride semiconductor material containing Al is provided covering an outer periphery of the active layer.

14. A semiconductor light emitting device comprising:

a growth substrate; and

a pillar-shaped semiconductor layer formed on the growth substrate,

wherein the pillar-shaped semiconductor layer has an n-type nanowire layer formed at a center, an active layer fanned on an outermore side than the n-type nanowire layer, and a p-type semiconductor layer formed on an outermore side than the active layer, and

wherein an outer surface protection layer made of a nitride semiconductor material containing Al is provided covering an outer periphery of a tunnel junction layer.

15. The semiconductor light emitting device according to claim 9 , wherein the inner surface protection layer is provided on a bottom part of the n-type nanowire layer.

16. The semiconductor light emitting device according to claim 9 , further comprising a buried semiconductor layer formed to cover the pillar-shaped semiconductor layer.

17. The semiconductor fight emitting device according to claim 9 , wherein a tunnel junction layer is formed on an outermore side than the p-type semiconductor layer.

18. A growth method of a semiconductor light emitting device comprising:

a mask process of forming a mask layer having an opening portion on a growth substrate; and

a growth process of forming a pillar-shaped semiconductor layer in the opening portion by using selective growth,

wherein the growth process comprises:

a process of forming an n-type nanowire layer,

a process of forming an active layer on an outermore side than the n-type nanowire layer,

a process of forming an inner surface protection layer in contact with lower sides of the n-type nanowire layer and the active layer, the inner surface protection layer being made of a nitride semiconductor material containing Al, and

a process of forming a p-type semiconductor layer on an outermoreside than the active layer.

Assignments (2)
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Oct 21, 2020
From: KAMIYAMA, SATOSHI; TAKEUCHI, TETSUYA; IWAYA, MOTOAKI; AKASAKI, ISAMU; WEIFANG, LU
To: KOITO MANUFACTURING CO., LTD.; MEIJO UNIVERSITY; TOYODA GOSEI CO., LTD.
Reel/Frame 054129/0107 →
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Sep 18, 2020
From: SONE, NAOKI; IIDA, KAZUYOSHI; NAKAMURA, RYO; OYA, MASAKI
To: KOITO MANUFACTURING CO., LTD.; MEIJO UNIVERSITY; TOYODA GOSEI CO., LTD.
Reel/Frame 053818/0362 →
Priority Claims (2)
JP JP2019-164083 · Sep 10, 2019 · national
JP JP2019-182829 · Oct 3, 2019 · national
Continuity (1)
Related Publication 20210074877A1 · Mar 11, 2021