Methods for independent memory bank maintenance and memory devices and systems employing the same
Provided herein are memory devices, systems including memory devices, and methods of operating memory devices in which multiple counters are provided to permit memory refresh commands greater freedom in targeting subsets of the memory device for data refresh operations. In one embodiment, a memory device is provided, comprising a plurality of memory banks, and circuitry configured to (i) store a plurality of values, each of the plurality of values corresponding to one of the plurality of memory banks; (ii) refresh first data stored in a first one of the plurality of memory banks; and (iii) update a first one of the plurality of values corresponding to the first one of the plurality of memory banks based at least in part on refreshing the first data.
1. A memory device comprising:
a plurality of memory cells; and
circuitry configured to:
store a plurality of values, each value of the plurality of values corresponding to a subset of memory cells of the plurality of memory cells, and
perform, with a first frequency, first maintenance operations on a first subset of memory cells of the plurality of memory cells;
update a first value of the plurality of values corresponding to the first subset of memory cells based at least in part on performing the first maintenance operations at the first frequency;
perform, with a second frequency different from the first frequency, second maintenance operations on a second subset of memory cells of the plurality of memory cells; and
update a second value of the plurality of values corresponding to the second subset of memory cells based at least in part on performing the second maintenance operations at the second frequency.
2. The memory device of claim 1 , wherein each of the plurality of values corresponds to an address in the corresponding subset of memory cells.
3. The memory device of claim 1 , wherein the first maintenance operation and the second maintenance operation each comprise a refresh operation.
4. The memory device of claim 1 , wherein the first maintenance operation and the second maintenance operation each comprise one of a refresh operation, a data state inversion operation, an overvoltaging operation, a wear-leveling operation, and a garbage collection operation.
5. The memory device of claim 1 , wherein the first maintenance operation is of a different kind than the second maintenance operation.
6. The memory device of claim 1 , wherein the first frequency and the second frequency correspond to a retention time, a susceptibility to imprint, or both, of the first subset of memory cells and the second subset of memory cells, respectively.
7. The memory device of claim 1 , wherein the first subset of memory cells and the second subset of memory cells have different retention times, different susceptibility to imprint, or both.
8. The memory device of claim 1 , wherein the plurality of memory cells comprise dynamic random access memory (DRAM) cells, ferroelectric random access memory (FeRAM) cells, magnetic random access memory (MRAM) cells, phase change memory (PCM) cells, or a combination thereof.
9. The memory device of claim 1 , wherein the first subset of memory cells and the second subset of memory cells comprise different kinds of memory cells.
10. The memory device of claim 1 , wherein the first subset of memory cells and the second subset of memory cells are comprised by a single integrated semiconductor die.
11. A method comprising:
performing a first maintenance operation on a first subset of a plurality of memory cells of a memory device at a first frequency; and
performing a second maintenance operation on a second subset of the plurality of memory cells of the memory device at a second frequency different from the first frequency.
12. The method of claim 11 , wherein each of the first maintenance operation and the second maintenance comprise a refresh operation.
13. The method of claim 11 , wherein each of the first maintenance operation and the second maintenance operation include one of a refresh operation, a data state inversion operation, an overvoltaging operation, a wear-leveling operation, and a garbage collection operation.
14. The method of claim 11 , wherein the first frequency and the second frequency correspond to a retention time, a susceptibility to imprint, or both, of the first subset and the second subset, respectively.
15. The method of claim 11 , wherein the first subset of memory cells and the second subset of memory cells have different retention times, different susceptibility to imprint, or both.
16. A memory device, comprising:
a plurality of memory cells; and
circuitry configured to:
perform a first maintenance operation on a first subset of the plurality of memory cells at a first frequency, and
perform a second maintenance operation on a second subset of the plurality of memory cells at a second frequency different from the first frequency.
17. The memory device of claim 16 , wherein each of the first maintenance operation and the second maintenance comprise a refresh operation.
18. The memory device of claim 16 , wherein the first frequency and the second frequency correspond to a retention time, a susceptibility to imprint, or both, of the first subset and the second subset, respectively.
19. The memory device of claim 16 , wherein the first subset and the second subset have different retention times, different susceptibility to imprint, or both.
20. The memory device of claim 16 , wherein the first subset and the second subset are comprised by a single integrated semiconductor die.