IP Library › Granted Patent US 11,538,907
Granted Patent B2
US 11,538,907 · App. 17/019,684 · Granted Dec 27, 2022

Semiconductor memory device and method of manufacturing the same

Inventor: Masakazu Goto (Yokkaichi Mie, JP)
Assignee: Kioxia Corporation
H01L29/1041H01L27/1157H01L27/11565H01L27/11582
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Quick Facts
Patent No.
US 11,538,907
App. No.
17/019,684
Granted
Dec 27, 2022
Kind
B2
Abstract

A semiconductor memory device includes first conducting layers and a first semiconductor layer opposed to the first conducting layers. If a concentration of the dopant in the first semiconductor layer is measured along an imaginary straight line, the concentration of the dopant has: a maximum value at a first point, a minimum value in a region closer to the first conducting layer than the first point at a second point; and a minimum value in a region farther from the first conducting layer than the first point at a third point. The second point is nearer to an end portion of the first semiconductor layer on the first conducting layer side than that on the opposite side. The third point is farther from the end portion on the first conducting layer side than that on the opposite side.

Claims (26)

1. A semiconductor memory device comprising:

a substrate;

a plurality of first conducting layers arranged in a first direction that intersects with a surface of the substrate;

a first semiconductor layer extending in the first direction, the first semiconductor layer being opposed to the plurality of first conducting layers in a second direction that intersects with the first direction and containing a dopant; and

memory cells disposed at intersecting portions between the first conducting layers and the first semiconductor layer, wherein

the first semiconductor layer contains crystal grains of 100 nm or more in size,

when a concentration of the dopant in the first semiconductor layer is measured along an imaginary straight line that extends in the second direction,

a point on the imaginary straight line at which the concentration of the dopant has a maximum value is defined as a first point,

a point on the imaginary straight line at which the concentration of the dopant has a minimum value in a region closer to the first conducting layer than the first point is defined as a second point, and

a point on the imaginary straight line at which the concentration of the dopant has a minimum value in a region farther from the first conducting layer than the first point is defined as a third point, wherein

a distance from the second point to an end portion of the first semiconductor layer on the first conducting layer side is smaller than a distance from the second point to an end portion of the first semiconductor layer on an opposite side of the first conducting layer, and

a distance from the third point to the end portion of the first semiconductor layer on the first conducting layer side is greater than a distance from the third point to the end portion of the first semiconductor layer on the opposite side of the first conducting layer.

2. The semiconductor memory device according to claim 1 , wherein

a distance from the first point to the end portion of the first semiconductor layer on the first conducting layer side is greater than a distance from the first point to the end portion of the first semiconductor layer on the opposite side of the first conducting layer.

3. The semiconductor memory device according to claim 1 , wherein

when a point on the imaginary straight line positioned between the first point and the second point is defined as a fourth point, and the concentration of the dopant has an intermediate value between the maximum value corresponding to the first point and the minimum value corresponding to the second point at the fourth point,

a point on the imaginary straight line positioned between the first point and the third point is defined as a fifth point, and the concentration of the dopant has an intermediate value between the maximum value corresponding to the first point and the minimum value corresponding to the third point at the fifth point,

a region of the first semiconductor layer closer to the first conducting layer than the fourth point is defined as a first region,

a region of the first semiconductor layer from the fourth point to the fifth point is defined as a second region, and

a region of the first semiconductor layer farther from the first conducting layer than the fifth point is defined as a third region,

an average value of the concentration of the dopant in the second region is greater than an average value of the concentration of the dopant in the first region, and

the average value of the concentration of the dopant in the second region is greater than an average value of the concentration of the dopant in the third region.

4. The semiconductor memory device according to claim 1 , wherein

the third point is positioned at the end portion of the first semiconductor layer on the opposite side of the first conducting layer.

5. The semiconductor memory device according to claim 1 , wherein

the dopant is carbon (C), oxygen (O), nitrogen (N), or boron (B).

Assignments (2)
CORRECTIVE ASSIGNMENT TO CORRECT THE ASSIGNEE NAME PREVIOUSLY RECORDED AT REEL: 053759 FRAME: 0364. ASSIGNOR(S) HEREBY CONFIRMS THE ASSIGNMENT. Recorded Oct 18, 2020
From: GOTO, MASAKAZU
To: KIOXIA CORPORATION
Reel/Frame 054106/0066 →
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Sep 14, 2020
From: GOTO, MASAKAZU
To: KIOXIA CORPOATION
Reel/Frame 053759/0364 →
Priority Claims (1)
JP JP2020-008477 · Jan 22, 2020 · national
Continuity (1)
Related Publication 20210226013A1 · Jul 22, 2021