Methods for forming three-dimensional memory devices with backside source contacts

1. A three-dimensional (3D) memory device, comprising:

a substrate;

a peripheral circuit above the substrate;

a memory stack comprising interleaved conductive layers and dielectric layers above the peripheral circuit;

an N-type doped semiconductor layer above the memory stack;

a plurality of channel structures each extending vertically through the memory stack into the N-type doped semiconductor layer, wherein upper ends of the plurality of channel structures are laterally surrounded by the N-type doped semiconductor layer;

a conductive layer in contact with the upper ends of the plurality of channel structures, wherein at least part of the conductive layer is on the N-type doped semiconductor layer; and

a source contact above the memory stack and in contact with the N-type doped semiconductor layer.

2. The 3D memory device of claim 1 , wherein the N-type doped semiconductor layer comprises polysilicon.

3. The 3D memory device of claim 1 , wherein the 3D memory device is configured to generate gate-induced-drain-leakage (GIDL)—assisted body biasing when performing an erase operation.

4. The 3D memory device of claim 1 , wherein each of the channel structures comprises a memory film and a semiconductor channel, and an upper end of the memory film is below an upper end of the semiconductor channel.

5. The 3D memory device of claim 4 , wherein the conductive layer comprises a metal silicide layer and a metal layer.

6. The 3D memory device of claim 5 , wherein the metal silicide layer is in contact with the semiconductor channel, and the metal layer is above and in contact with the metal silicide layer.

7. The 3D memory device of claim 4 , wherein a portion of the semiconductor channel extending into the N-type doped semiconductor layer comprises doped polysilicon.

8. The 3D memory device of claim 1 , wherein a thickness of the N-type doped semiconductor layer is less than about 50 nm.

9. The 3D memory device of claim 1 , further comprising an interconnect layer above and electrically connected to the source contact.

10. The 3D memory device of claim 9 , further comprising a first contact through the N-type doped semiconductor layer, wherein the N-type doped semiconductor layer is electrically connected to the peripheral circuit through at least the source contact, the interconnect layer, and the first contact.

11. The 3D memory device of claim 10 , further comprising a second contact through the N-type doped semiconductor layer, wherein the interconnect layer comprises a contact pad electrically connected to the second contact.

12. The 3D memory device of claim 1 , further comprising an insulating structure extending vertically through the memory stack and extending laterally to separate the plurality of channel structures into a plurality of blocks, wherein a top surface of the insulating structure is flush with a bottom surface of the N-type doped semiconductor layer.

13. The 3D memory device of claim 1 , further comprising a bonding interface between the peripheral circuit and the memory stack.

14. The 3D memory device of claim 1 , wherein an upper end of each of the plurality of channel structures is flush with or below a top surface of the N-type doped semiconductor layer.

15. A three-dimensional (3D) memory device, comprising:

a substrate;

a memory stack comprising interleaved conductive layers and dielectric layers above the substrate;

an N-type doped semiconductor layer above the memory stack;

a plurality of channel structures each extending vertically through the memory stack into the N-type doped semiconductor layer, wherein upper ends of the plurality of channel structures are laterally surrounded by the N-type doped semiconductor layer, each of the plurality of channel structures comprises a memory film and a semiconductor channel, an upper end of the memory film being below an upper end of the semiconductor channel; and

a conductive layer in contact with the semiconductor channels of the plurality of channel structures, wherein at least part of the conductive layer is on the N-type doped semiconductor layer.

16. The 3D memory device of claim 15 , wherein the conductive layer comprises a metal silicide layer and a metal layer.

17. The 3D memory device of claim 16 , wherein the metal silicide layer is in contact with the semiconductor channel, and the metal layer is above and in contact with the metal silicide layer.

18. The 3D memory device of claim 16 , wherein the metal layer is in contact with the semiconductor channel, and part of the metal layer is above and in contact with the metal silicide layer.

19. The 3D memory device of claim 15 , further comprising an insulating structure extending vertically through the memory stack and extending laterally to separate the plurality of channel structures into a plurality of blocks, wherein a top surface of the insulating structure is flush with a bottom surface of the N-type doped semiconductor layer.

20. A three-dimensional (3D) memory device, comprising:

a first semiconductor structure comprising a peripheral circuit;

a second semiconductor structure comprising:

a memory stack comprising interleaved conductive layers and dielectric layers;

an N-type doped semiconductor layer;

a plurality of channel structures each extending vertically through the memory stack into the N-type doped semiconductor layer and electrically connected to the peripheral circuit, wherein upper ends of the plurality of channel structures are laterally surrounded by the N-type doped semiconductor layer; and

a conductive layer comprising a metal silicide layer and a metal layer electrically connecting the plurality of channel structures, and

a bonding interface between the first semiconductor structure and the second semiconductor structure.