Semiconductor memory device

1. A semiconductor memory device comprising:

a substrate; and

a first memory layer disposed above the substrate in a first direction that intersects with a surface of the substrate, wherein

the first memory layer includes:

a plurality of first conducting layers arranged in the first direction and extending in a second direction that intersects with the first direction;

a plurality of first insulating layers disposed between the respective plurality of first conducting layers;

a plurality of second conducting layers separated from the plurality of first conducting layers in a third direction that intersects with the first direction and the second direction, the plurality of second conducting layers being arranged in the first direction and extending in the second direction;

a plurality of second insulating layers disposed between the respective plurality of second conducting layers; and

a first semiconductor layer that includes a first part, a second part, and a third part, the first part extending in the first direction and opposing the plurality of first conducting layers and the plurality of first insulating layers, the second part extending in the first direction and opposing the plurality of second conducting layers and the plurality of second insulating layers, and the third part being connected to the first part and the second part and positioned farther from the substrate than the first part and the second part, and

when:

a cross-sectional surface extending in the second direction and the third direction and including at least a part of the third part is defined as a first cross-sectional surface;

a region of the third part on one side in the third direction with respect to a first imaginary center line in the third direction in the first cross-sectional surface is defined as a first region, and a region on the other side is defined as a second region;

the first imaginary center line is an imaginary line extending in the second direction and passing through a position at a half of a maximum width in a part where a width in the third direction of the third part in the first cross-sectional surface is maximum; and

in the first cross-sectional surface,

the third part has a maximum width in the second direction in the first region defined as a first width,

the third part has a maximum width in the second direction in the second region defined as a second width, and

the third part has a width in the second direction on the first imaginary center line defined as a third width,

the third width is smaller than the first width, and

the third width is smaller than the second width.

2. The semiconductor memory device according to claim 1 , further comprising

a second memory layer disposed above the first memory layer in the first direction, wherein

the second memory layer includes:

a plurality of third conducting layers arranged in the first direction and extending in the second direction;

a plurality of third insulating layers disposed between the respective plurality of third conducting layers;

a plurality of fourth conducting layers separated from the plurality of third conducting layers in the third direction, the plurality of fourth conducting layers being arranged in the first direction and extending in the second direction;

a plurality of fourth insulating layers disposed between the respective plurality of fourth conducting layers; and

a second semiconductor layer that includes a fourth part, a fifth part, and a sixth part, the fourth part extending in the first direction and opposing the plurality of third conducting layers and the plurality of third insulating layers, the fifth part extending in the first direction and opposing the plurality of fourth conducting layers and the plurality of fourth insulating layers, and the sixth part being connected to the fourth part and the fifth part, and

the sixth part is in contact with the third part.

3. The semiconductor memory device according to claim 2 , wherein

the second semiconductor layer includes a seventh part connected to the fourth part and the fifth part, the seventh part is positioned in the first direction with respect to the sixth part, and

when:

a cross-sectional surface extending in the second direction and the third direction and including at least a part of the seventh part is defined as a second cross-sectional surface;

a region of the seventh part on one side in the third direction with respect to a second imaginary center line in the third direction in the second cross-sectional surface is defined as a third region, and a region on the other side is defined as a fourth region;

the second imaginary center line is an imaginary line extending in the second direction and passing through a position at a half of a maximum width in a part where a width in the third direction of the seventh part in the second cross-sectional surface is maximum; and

in the second cross-sectional surface,

the seventh part has a maximum width in the second direction in the third region defined as a fourth width,

the seventh part has a maximum width in the second direction in the fourth region defined as a fifth width, and

the seventh part has a width in the second direction on the second imaginary center line defined as a sixth width,

the sixth width is smaller than the fourth width, and

the sixth width is smaller than the fifth width.

4. The semiconductor memory device according to claim 1 ,

when:

a distance in the third direction between a surface on one side in the third direction and a surface on the other side in the third direction of the first part is defined as a first distance; and

a distance in the third direction between a surface on one side in the third direction and a surface on the other side in the third direction of the second part is defined as a second distance,

a width in the third direction of the third part is larger than a sum of the first distance and the second distance.

5. A semiconductor memory device comprising:

a substrate;

a first memory layer disposed above the substrate in a first direction that intersects with a surface of the substrate; and

a second memory layer disposed above the first memory layer in the first direction, wherein

the first memory layer includes:

a plurality of first conducting layers arranged in the first direction and extending in a second direction that intersects with the first direction;

a plurality of first insulating layers disposed between the respective plurality of first conducting layers;

a plurality of second conducting layers separated from the plurality of first conducting layers in a third direction that intersects with the first direction and the second direction, the plurality of second conducting layers being arranged in the first direction and extending in the second direction;

a plurality of second insulating layers disposed between the respective plurality of second conducting layers;

a first semiconductor layer that includes a first part, a second part, and a third part, the first part extending in the first direction and opposing the plurality of first conducting layers and the plurality of first insulating layers, the second part extending in the first direction and opposing the plurality of second conducting layers and the plurality of second insulating layers, and the third part being connected to the first part and the second part; and

a third insulating layer disposed between the first part and the second part and extending in the first direction and the second direction,

the second memory layer includes:

a plurality of third conducting layers arranged in the first direction and extending in the second direction;

a plurality of fourth insulating layers disposed between the respective plurality of third conducting layers;

a plurality of fourth conducting layers separated from the plurality of third conducting layers in the third direction, the plurality of fourth conducting layers being arranged in the first direction and extending in the second direction;

a plurality of fifth insulating layers disposed between the respective plurality of fourth conducting layers;

a second semiconductor layer that includes a fourth part, a fifth part, and a sixth part, the fourth part extending in the first direction and opposing the plurality of third conducting layers and the plurality of fourth insulating layers, the fifth part extending in the first direction and opposing the plurality of fourth conducting layers and the plurality of fifth insulating layers, and the sixth part being connected to the fourth part and the fifth part, and

a sixth insulating layer disposed between the fourth part and the fifth part and extending in the first direction and the second direction,

the sixth part is connected to the third part,

the sixth insulating layer includes:

a seventh part disposed on the first memory layer side with respect to the plurality of third conducting layers and the plurality of fourth conducting layers, the seventh part having a first width in the third direction;

an eighth part disposed on the first memory layer side with respect to the seventh part, the eighth part having a second width in the third direction; and

a ninth part disposed on the first memory layer side with respect to the eighth part, the ninth part having a third width in the third direction,

the second width is larger than the first width, and

the second width is larger than the third width.

6. The semiconductor memory device according to claim 5 , wherein

the second memory layer further includes a third semiconductor layer disposed on the first memory layer side with respect to the plurality of third conducting layers and the plurality of fourth conducting layers, the third semiconductor layer extends in the second direction, and

when:

a surface of the third semiconductor layer on the first memory layer side in the first direction is defined as a first surface, and

a surface of the third semiconductor layer on an opposite side of the first memory layer in the first direction is defined as a second surface,

the eighth part is closer to the first memory layer than the second surface and farther from the first memory layer than the first surface.