Interposer for hybrid interconnect geometry
An electronic device and associated methods are disclosed. In one example, the electronic device includes a substrate, a semiconductor die thereon, electrically coupled to the substrate, and an interposer adapted to connect the substrate to a circuit board. The interposer can include a major surface, a recess in the major surface, a first plurality of interconnects passing through the interposer within the recess to electrically couple the substrate to a circuit board, and a second plurality of interconnects on the major surface of the interposer to electrically couple the substrate to the circuit board, wherein each of the second plurality of interconnects comprises a smaller cross-section than some of the first plurality of interconnects.
1. A semiconductor device comprising:
a substrate;
a semiconductor die thereon, electrically coupled to the substrate;
an interposer adapted to connect the substrate to a circuit board, the interposer comprising:
a major surface;
a recess in a central portion of the major surface;
a first plurality of interconnects passing through the interposer within the recess to electrically couple the substrate to the circuit board, wherein each of the first plurality of interconnects comprises a diameter of about 5 to about 15 mils;
a second plurality of interconnects on the major surface of the interposer to electrically couple the substrate to the circuit board, wherein each of the second plurality of interconnects comprises a smaller cross-section than some of the first plurality of interconnects, wherein each of the second plurality of interconnects comprises a diameter of about 1 to about 4 mils.
2. The device of claim 1 , wherein the first and second plurality of interconnects each comprise a ball grid array.
3. The device of claim 1 , further comprising a shield layer in the interposer isolated from the first and second plurality of interconnects.
4. The device of claim 1 , wherein the interposer further comprises metallic traces, vertical via, metallic pads, or combinations thereof.
5. The device of claim 1 , wherein the second plurality of interconnects are on the major surface near one or more edges of the interposer.
6. A semiconductor device comprising:
a substrate;
a semiconductor die thereon, electrically coupled to the substrate;
an interposer adapted to connect the substrate to a circuit board, the interposer comprising:
a major surface;
a recess in the major surface, one or more passive components disposed in the recess;
a first plurality of interconnects passing through the interposer within the recess to electrically couple the substrate to the circuit board;
a second plurality of interconnects on the major surface of the interposer to electrically couple the substrate to the circuit board, wherein each of the second plurality of interconnects comprises a smaller cross-section than some of the first plurality of interconnects.
7. The device of claim 6 , wherein the one or more passive components comprise one or more capacitors.
8. The device of claim 7 , wherein the one or more capacitors are coupled between a ground plane, and one or more power planes.
9. The device of claim 7 , wherein the one or more capacitors are at least partially embedded in the interposer.
10. A semiconductor device comprising:
a substrate;
a semiconductor die thereon, electrically coupled to the substrate;
an interposer adapted to connect the substrate to a circuit board, the interposer comprising:
a major surface;
a recess in the major surface;
a first plurality of interconnects passing through the interposer within the recess to electrically couple the substrate to the circuit board;
a second plurality of interconnects on the major surface of the interposer to electrically couple the substrate to the circuit board, wherein each of the second plurality of interconnects comprises a smaller cross-section than some of the first plurality of interconnects,
a second surface opposite the major surface, the second surface proximate the circuit board;
a second recess in the second surface, the second recess opposite the first recess, wherein the first recess is proximate the substrate, and the second recess is proximate the circuit board;
a third plurality of interconnects in the second recess, wherein the first plurality of interconnects in the first recess are electrically coupled to the third plurality of interconnects in the second recess through the interposer.
11. The device of claim 10 , wherein the first plurality of interconnects in the first recess are electrically coupled to the third plurality of interconnects by a conductive layer comprising metallic traces, vertical via, metallic pads, or combinations thereof.
12. The device of claim 10 , wherein the first plurality of interconnects in the first recess are electrically coupled to the third plurality of interconnects by one or more capacitors.