Semiconductor memory device including a first electrode to input command set and output read data and a second electrode to supply power
A semiconductor memory device includes: a memory cell array; a peripheral circuit connected to this memory cell array, the peripheral circuit outputting data in the memory cell array as a read data in response to input of a command set, the command set including a first command, address data, and a second command; a first electrode capable of being used in input of the command set and output of the read data; and a second electrode capable of supplying electric power to the peripheral circuit. A current flowing in the second electrode at a second timing is larger than a current flowing in the second electrode at a first timing, the first timing being a timing at which the first command is inputted, the second timing being a timing before which the input of the address data is started and after which an input of the second command is finished.
1. A semiconductor device, comprising:
a first electrode;
a peripheral circuit connected to the first electrode and outputting data from the first electrode in response to input of a command set, the command set including a first command, address data inputted after an input of the first command, and a second command inputted after an input of the address data; and
a second electrode capable of supplying electric power to the peripheral circuit, wherein
a current flowing in the second electrode at a second timing is larger than a current flowing in the second electrode at a first timing, the first timing being a timing at which the first command is inputted, the second timing being a timing after the input of the address data is started and before an input of the second command is finished.
2. The semiconductor device according to claim 1 , wherein
the second timing is a certain timing after the input of the address data is finished and before the input of the second command is finished.
3. The semiconductor device according to claim 1 , wherein
the second timing is a certain timing after the input of the address data is started and before the input of the address data is finished.
4. The semiconductor device according to claim 1 , wherein
a first average value is an average value of a current flowing in the second electrode after the input of the first command is finished and before the input of the address data is started; and
a second average value is an average value of a current flowing in the second electrode after the input of the address data is finished and before the input of the second command is started, and wherein
the second average value is larger than the first average value.
5. A semiconductor device, comprising:
a first electrode;
a peripheral circuit connected to the first electrode and outputting data from the first electrode in response to input of a command set, the command set including a first command, address data inputted after an input of the first command and including a flag information, and a second command inputted after an input of the address data; and
a second electrode capable of supplying electric power to the peripheral circuit, wherein
in a case that the flag information is a first value,
a first current flowing in the second electrode at a first timing at which the first command is inputted,
a second current flows in the second electrode at a second timing after the input of the first command is finished and before an input of the second command is finished, and
a third current flows in the second electrode at a third timing after the input of the second command is finished;
in a case that the flag information is a second value,
a fourth current flows in the second electrode at the first timing,
a fifth current flows in the second electrode at the second timing, and
a sixth current flows in the second electrode at the third timing; and
the third current, the fifth current, and the sixth current are larger than the first current, the second current, and the fourth current.
6. The semiconductor device according to claim 5 ,
further comprising a data bus through which data is transferred,
in a case that the flag information is the first value, a setup of the data bus is started after the input of the second command is finished,
in a case that the flag information is the second value, the setup of the data bus is started before the input of the second command is finished.
7. A system comprising a plurality of chips,
each of the plurality of chips comprising:
a first electrode;
a peripheral circuit connected to the first electrode and outputting data from the first electrode in response to input of a command set, the command set including a first command, address data inputted after an input of the first command and including a flag information, and a second command inputted after an input of the address data; and
a second electrode capable of supplying electric power to the peripheral circuit, wherein
the plurality of chips include a first chip and a second chip,
at a first timing at which the first command is inputted to the first chip and the second chip, a first current flows in the second electrode of the first chip, and a second current flows in the second electrode of the second chip,
at a second timing after the input of the address data is started and before the input of the address data is finished, a third current flows in the second electrode of the first chip, and a fourth current flows in the second electrode of the second chip,
at a third timing after the input of the address data is finished and before the input of the second command is started, a fifth current flows in the second electrode of the first chip, and a sixth current flows in the second electrode of the second chip,
the third current, the fourth current, and the fifth current are larger than the first current, the second current, and the sixth current.