High bandwidth controller memory buffer (CMB) for peer to peer data transfer
A PCIe architecture is disclosed incorporating a controller memory buffer (CMB). Write data is written to the CMB and is not read out for processing upon receiving a write command for the write data. The data is read out of the CMB and processed to obtain processed data upon receiving feedback from a NAND channel controller. The processed data may be written directly to the NAND channel controller or may be written to a light write buffer that is read by the NAND channel controller. The processed data may be written to a light write buffer functioning as a cut through buffer.
1. A method comprising:
(a) receiving, by a storage device controller, write data;
(b) storing, by the storage device controller, the write data in a control memory buffer (CMB);
(c) receiving, by the storage device controller, a write command for the write data after (a);
(d) after (c), refraining, by the storage device controller, from processing the write command until a ready signal is received, the ready signal indicating that a storage device is ready to receive data;
(e) receiving, by the storage device controller, the ready signal;
(f) after (e), processing, by the storage device controller, the write data in the control memory buffer to obtain processed data;
(g) writing, by the storage device controller, the processed data to the storage device;
after performing (f) and at least one of before and during performing (g), writing the processed data to a light write buffer (LWB) that is implemented on a different memory device than the CMB; and
wherein (g) further comprises reading, by the storage device, the processed data from the LWB.
2. The method of claim 1 , wherein the storage device is a NAND flash storage device and wherein the ready signal is received from a NAND channel controller coupled to the NAND flash storage device, the ready signal indicating that the NAND flash storage device is ready to be programmed.
3. The method of claim 1 , wherein (c) through (g) are performed without writing the processed data to any memory device.
4. The method of claim 1 , wherein the CMB is implemented using dynamic random access memory (DRAM) and the LWB is implemented using static random access memory (SRAM).
5. The method of claim 1 , wherein the CMB is implemented using dynamic random access memory (DRAM) and the LWB is implemented using on-chip registers of the storage device controller.
6. The method of claim 1 , wherein the LWB is smaller than the CMB.
7. The method of claim 6 , wherein a depth of the LWB is less than one tenth a depth of the CMB.
8. The method of claim 1 , further comprising using the LWB as a cut through buffer.
9. The method of claim 1 , wherein the storage device controller is a solid state device (SSD) controller implementing the PCIe (peripheral component interconnect express) protocol and is coupled to a PCIe fabric, the write command being received from a component coupled to the PCIe fabric.
10. A system comprising:
a storage device;
a storage controller coupled to the storage device;
a first memory implementing a control memory buffer (CMB), the first memory being coupled to the storage controller and;
a second memory different from the first memory and implementing a light write buffer (LWB);
wherein the storage controller is programmed to:
(a) receive write data;
(b) store the write data in a control memory buffer (CMB);
(c) receive a write command for the write data after (a);
(d) after (c), refrain from processing the write command until a ready signal is received, the ready signal indicating that a storage device is ready to receive data;
(e) receive the ready signal;
(f) after (e), process the write data in the control memory buffer to obtain processed data;
(g) write the processed data to the storage device and;
after performing (f) and at least one of before and during performing (g), write the processed data to the LWB; and
wherein storage device is programmed to perform (g) by reading the processed data from the LWB.
11. The system of claim 10 , wherein the storage device is a NAND flash storage device programmed to output the ready signal when a die of the NAND flash storage device is ready to be programmed.
12. The system of claim 10 , wherein the storage controller is programmed to perform (c) through (g) without writing the processed data to the first memory implementing the CMB.
13. The system of claim 10 , wherein the first memory is a dynamic random access memory (DRAM) and the second memory is a static random access memory (SRAM).
14. The system of claim 10 , wherein the first memory is a dynamic random access memory (DRAM) and the second memory is implemented using on-chip registers of the storage controller.
15. The system of claim 10 , wherein the LWB is smaller than the CMB.
16. The system of claim 15 , wherein a depth of the LWB is less than a depth of the CMB.
17. The system of claim 10 , wherein the LWB is a cut through buffer.
18. The system of claim 10 , wherein the storage controller is a solid state device (SSD) controller implementing the PCIe (peripheral component interconnect express) protocol, the system further comprising a PCIe fabric and a component coupled to the PCIe fabric and programmed to output the write data and the write command.