Secure boot of a processing chip via hardware memory configuration
Techniques in electronic systems, such as in systems including a processing chip and one or more external memory chips, provide improvements in one or more of system security, performance, cost, and efficiency. In some embodiments, the processing chip includes immutable hardware that is enabled, without a use of any CPUs, to determine and/or confirm an expected configuration of one or more external memory chips (such as with a Serial Presence Detect operation), and/or to enable communication with the one or more external memory chips. The immutable hardware is further enabled to copy executable code from a non-volatile one of the one or more external memory chips to another of the one or more external memory chips so that a CPU of the processing chip is able to securely boot by fetching initial instructions from the copy of the executable code.
1. A method for securely booting a processing chip, comprising:
using immutable hardware of the processing chip and in response to de-assertion of a reset signal, continuing to hold one or more run-time programmable processors in the processing chip in a respective reset state;
performing, via the immutable hardware, Serial Presence Detect (SPD) to determine or confirm presence of a non-volatile memory chip on a first external memory interface of the processing chip and presence of at least one other memory chip on a second external memory interface of the processing chip;
copying, via the immutable hardware, executable code stored in the non-volatile memory chip to the at least one other memory chip, wherein data read from the non-volatile memory chip by the copying is encrypted with a key that is accessible solely to the immutable hardware;
subsequent to the copying, releasing, via the immutable hardware, a particular one of the one or more run-time programmable processors from the respective reset state;
enabling, via the immutable hardware, the particular one of the one or more run-time programmable processors to complete an initial instruction fetch referencing the copy of the executable code in the at least one other memory chip;
decrypting data read from the at least one other memory chip to provide instructions to complete the initial instruction fetch; and
creating the key at a manufacturing time of the processing chip using a physically unclonable function in the processing chip.
2. The method of claim 1 , wherein the method further comprises:
configuring, via the immutable hardware, the first external memory interface and the non-volatile memory chip to communicate; and
configuring, via the immutable hardware, the second external memory interface and the at least one other memory chip to communicate.
3. The method of claim 1 , wherein the executable code comprises a bootloader.
4. The method of claim 3 , wherein the bootloader comprises a basic input/output system (BIOS) or unified extensible firmware interface (UEFI) firmware.
5. The method of claim 3 , wherein the executable code comprises an operating system kernel.
6. The method of claim 1 , wherein the one or more run-time programmable processors are unable to access the non-volatile memory chip.
7. The method of claim 1 , wherein the one or more run-time programmable processors are the only run-time programmable processors in the processing chip.
8. A system, comprising:
a processing chip comprising: one or more run-time-programmable processors, immutable hardware, a first external memory interface, and a second external memory interface;
a non-volatile boot storage coupled to the first external memory interface, wherein the non-volatile boot storage is external to the processing chip; and
at least one other memory chip coupled to the second external memory interface, wherein the at least one other memory chip is external to the processing chip, and
wherein the processing chip is configured to:
using the immutable hardware and in response to de-assertion of a reset signal, continue to hold the one or more run-time programmable processors in a respective reset state;
perform, via the immutable hardware, Serial Presence Detect (SPD) to determine or confirm presence of the non-volatile boot storage on the first external memory interface and presence of the at least one other memory chip on the second external memory interface;
copy, via the immutable hardware, executable code stored in the non-volatile boot storage to the at least one other memory chip, wherein data read from the non-volatile boot storage by the copying is encrypted with a key that is accessible solely to the immutable hardware, and wherein the key is created at a manufacturing time of the processing chip using a physically unclonable function in the processing chip;
subsequent to the copying, release, via the immutable hardware, a particular one of the one or more run-time programmable processors from the respective reset state; and
enable, via the immutable hardware, the particular one of the one or more run-time programmable processors to complete an initial instruction fetch referencing the copy of the executable code in the at least one other memory chip; and
decrypt data read from the at least one other memory chip to provide instructions to complete the initial instruction fetch.
9. An integrated circuit, comprising:
a first external memory interface configured to couple to a non-volatile memory chip, wherein the non-volatile memory chip is external to the integrated circuit;
a second external memory interface configured to couple to at least one other memory chip, wherein the at least one other memory chip is external to the integrated circuit;
one or more run-time-programmable processors; and
immutable hardware coupled to the first external memory interface and the second external memory interface, wherein the integrated circuit is configured to:
using the immutable hardware and in response to de-assertion of a reset signal, continue to hold the one or more run-time programmable processors in a respective reset state;
perform, via the immutable hardware, Serial Presence Detect (SPD) to determine or confirm presence of the non-volatile memory chip on the first external memory interface and presence of the at least one other memory chip on the second external memory interface;
copy, via the immutable hardware, executable code stored in the non-volatile memory chip to the at least one other memory chip, wherein data read from the non-volatile memory chip by the copying is encrypted with a key that is accessible solely to the immutable hardware, and wherein the key is created at a manufacturing time of the integrated circuit using a physically unclonable function in the integrated circuit;
subsequent to the copying, release, via the immutable hardware, a particular one of the one or more run-time programmable processors from the respective reset state; and
enable, via the immutable hardware, the particular one of the one or more run-time programmable processors to complete an initial instruction fetch referencing the copy of the executable code in the at least one other memory chip; and
decrypt data read from the at least one other memory chip to provide instructions to complete the initial instruction fetch.
10. The integrated circuit of claim 9 , wherein the integrated circuit is configured to:
configure, via the immutable hardware, the first external memory interface and the non-volatile memory chip to communicate; and
configure, via the immutable hardware, the second external memory interface and the at least one other memory chip to communicate.
11. The integrated circuit of claim 9 , wherein the executable code comprises a bootloader.
12. The integrated circuit of claim 11 , wherein the bootloader comprises a basic input/output system (BIOS) or unified extensible firmware interface (UEFI) firmware.
13. The integrated circuit of claim 11 , wherein the executable code comprises an operating system kernel.
14. The integrated circuit of claim 9 , wherein the one or more run-time programmable processors are unable to access the non-volatile memory chip.