IP Library › Granted Patent US 11,432,406
Granted Patent B2
US 11,432,406 · App. 17/025,939 · Granted Aug 30, 2022

Package substrate

Inventors: Wu Chou Hsu (Kaohsiung, TW); Hsing Kuo Tien (Kaohsiung, TW); Chih-Cheng Lee (Kaohsiung, TW); Min-Yao Chen (Kaohsiung, TW)
Assignee: ADVANCED SEMICONDUCTOR ENGINEERING, INC.
H05K3/30H01L21/4857H01L23/49822H01L23/49827H01L23/544H05K1/0266H05K1/183H01L2223/54426H05K2201/1003H05K2203/166
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Quick Facts
Patent No.
US 11,432,406
App. No.
17/025,939
Granted
Aug 30, 2022
Kind
B2
Abstract

A package substrate and manufacturing method thereof are provided. The package substrate includes a substrate and an electronic component. The substrate includes a cavity. The electronic component is disposed in the cavity. The electronic component includes a first region and a second region, and an optical recognition rate of the first region is distinct from that of the second region.

Claims (35)

1. A package substrate, comprising:

a substrate including a cavity; and

an electronic component disposed in the cavity, wherein the electronic component includes a first region and a second region, and an optical recognition rate of the first region is distinct from that of the second region;

wherein the electronic component comprises a magnetic layer, a conductive wire in the magnetic layer and a stack of a first layer and a second layer, wherein the first layer is between the second layer and the magnetic layer, and wherein the second layer includes a protrusion inserted into the first layer to form the first region and the second region.

2. The package substrate of claim 1 , wherein the first layer comprises a passivation layer, and the second layer comprises a dielectric layer.

3. The package substrate of claim 1 , wherein the protrusion is further inserted into the magnetic layer.

4. The package substrate of claim 1 , further comprising:

a fiducial mark on the substrate; and

a conductive trace disposed on the electronic component and electrically connected to the conductive wire.

5. The package substrate of claim 1 ,

wherein the first layer comprises a first passivation layer covering over a first surface of the magnetic layer, and is formed with at least one indication region that exposes a selected portion of the magnetic layer.

6. The package substrate of claim 5 , wherein the covered region of the magnetic layer by the first passivation layer has an optical recognition rate different from that of the exposed portion of the magnetic layer through the indication region.

7. The package substrate of claim 6 , further comprising a fiducial mark arranged at a planar corner region thereof.

8. The package substrate of claim 7 , wherein the second layer comprises a dielectric layer and having a coverage that extends from the fiducial mark of the substrate to the indication region of the electronic component.

9. The package substrate of claim 8 , wherein the dielectric layer further extends into the cavity around the electronic component and configured to fix the electronic component in the cavity.

10. The package substrate of claim 8 , further comprising a conductive trace arranged on the dielectric layer, extending over the substrate and the electronic component, wherein the conductive trace extends into the dielectric layer and establishes an electrical contact with the conductive wire.

11. The package substrate of claim 10 , wherein the dielectric layer extends through the first passivation layer, surrounds the conductive trace, and contacts the conductive wire.

12. The package substrate of claim 8 , wherein the dielectric layer extends through the first passivation layer and into a recess in the magnetic layer to divide the electronic component into two inductive regions.

13. The package substrate of claim 10 , wherein the electronic component further comprises a second passivation layer covering a second surface of the magnetic layer opposite to the first surface thereof.

14. The package substrate of claim 13 , wherein the second passivation layer is provided with at least one recess that extends into the magnetic layer to expose a portion of the conductive wire.

15. The package substrate of claim 14 , further comprising an additional conductive trace that extends through the second passivation layer and establishes an electrical contact with the conductive wire.

16. The package substrate of claim 5 , wherein the indication region of the first passivation layer comprises a geometric pattern arranged over a planar corner region of the magnetic layer.

17. The package substrate of claim 16 , wherein a depth of the indication region is substantially the same as a thickness of the first passivation layer.

18. The package substrate of claim 16 , wherein a depth of the indication region is substantially greater than a thickness of the first passivation layer.

19. A package substrate, comprising:

a substrate including a cavity;

an electronic component disposed in the cavity, wherein the electronic component includes a first region and a second region, and an optical recognition rate of the first region is distinct from that of the second region;

a fiducial mark arranged at a planar corner region of the substrate; and

a conductive trace;

wherein the electronic component includes:

a magnetic layer with at least one conductive wire embedded therein;

a passivation layer covering over a surface of the magnetic layer, wherein the passivation layer is formed with at least one indication region that exposes a selected portion of the magnetic layer, and wherein the covered region of the magnetic layer by the passivation layer has an optical recognition rate different from that of the exposed portion of the magnetic layer through the indication region; and

a dielectric layer having a coverage that extends from the fiducial mark of the substrate to the indication region of the electronic component, wherein the dielectric layer further extends into the cavity around the electronic component and configured to fix the electronic component in the cavity;

wherein the conductive trace is arranged on the dielectric layer, extending over the substrate and the electronic component; and

wherein the conductive trace extends into the dielectric layer and establishes an electrical contact with the conductive wire.

Assignments (1)
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Sep 19, 2020
From: HSU, WU CHOU; TIEN, HSING KUO; LEE, CHIH-CHENG; CHEN, MIN-YAO
To: ADVANCED SEMICONDUCTOR ENGINEERING, INC.
Reel/Frame 053823/0856 →
Continuity (1)
Related Publication 20220095462A1 · Mar 24, 2022