Semiconductor device and manufacturing method thereof
In a method of manufacturing a negative capacitance structure, a dielectric layer is formed over a substrate. A first metallic layer is formed over the dielectric layer. After the first metallic layer is formed, an annealing operation is performed, followed by a cooling operation. A second metallic layer is formed. After the cooling operation, the dielectric layer becomes a ferroelectric dielectric layer including an orthorhombic crystal phase. The first metallic film includes a oriented crystalline layer.
1. A semiconductor device, comprising:
a fin structure including a channel region protruding from an isolation insulating layer;
a ferroelectric dielectric layer disposed over the channel layer; and
a conductive layer comprising a (111) oriented crystalline layer; and
a gate electrode layer disposed over the conductive layer,
wherein the conductive layer includes a TiN layer doped with Si, and comprises a (111) oriented crystalline structure.
2. The semiconductor device of claim 1 , wherein the ferroelectric dielectric layer includes a HfZrO 2 layer comprising a (111) oriented orthorhombic crystal.
3. The semiconductor device of claim 2 , wherein the ferroelectric dielectric layer includes Ti in an amount of 2-5 mol %.
4. The semiconductor device of claim 2 , wherein the ferroelectric dielectric layer includes Al in an amount of 5-7 mol %.
5. The semiconductor device of claim 2 , wherein a thickness of the ferroelectric dielectric layer is in a range from 1.0 nm to 5 nm.
6. A semiconductor device, comprising:
a channel layer made of a semiconductor;
an interfacial layer disposed on the channel layer;
a seed layer disposed on the interfacial layer;
a ferroelectric dielectric layer disposed over the seed layer; and
a gate electrode layer disposed over the ferroelectric dielectric layer,
wherein the ferroelectric dielectric layer comprises a (111) oriented orthorhombic crystal.
7. The semiconductor device of claim 6 , wherein the ferroelectric dielectric layer includes HfO 2 doped with one or more selected from the group consisting of Si, Zr, Al, La, Y, Gd and Sr.
8. The semiconductor device of claim 6 , wherein the ferroelectric dielectric layer includes HfZrO 2 .
9. The semiconductor device of claim 6 , wherein the seed layer includes ZrO 2 .
10. The semiconductor device of claim 6 , further comprising an upper crystal structure control layer between the ferroelectric dielectric layer and the gate electrode.
11. The semiconductor device of claim 10 , wherein the upper crystal structure control layer includes crystal grains that are (111) and (220) oriented.
12. The semiconductor device of claim 10 , wherein the upper crystal structure control layer includes Si-doped TiN.
13. The semiconductor device of claim 8 , wherein the ferroelectric dielectric layer further includes Ti in an amount of 2-5 mol %.
14. The semiconductor device of claim 8 , wherein the semiconductor device is an n-type FET and a work function adjustment layer including Al is disposed between the ferroelectric dielectric layer and the gate electrode layer.
15. The semiconductor device of claim 14 , wherein the ferroelectric dielectric layer further includes Al in an amount of 5-7 mol %.
16. The semiconductor device of claim 6 , wherein the interfacial layer is a silicon oxide layer having a thickness in a range from 0.5 nm to 1.5 nm.
17. A negative capacitance fin field effect transistor (NC-FinFET), comprising:
a fin structure including a channel region protruding from an isolation insulating layer;
an interfacial layer disposed over the channel region;
a ferroelectric dielectric layer disposed over the channel layer; and
a conductive layer comprising a (111) oriented crystalline layer; and
a gate electrode layer disposed over the conductive layer,
wherein
at least one of a bottom crystal structure control layer in contact with and between the interfacial layer and the ferroelectric dielectric layer and an upper crystal structure control layer in contact with and between the ferroelectric dielectric layer and the gate electrode is provided.
18. The semiconductor device of claim 17 , wherein the conductive layer includes a TiN layer doped with Si.
19. The semiconductor device of claim 18 , wherein the bottom crystal structure control layer is disposed between the interfacial layer and the ferroelectric dielectric layer, and includes ZrO 2 .
20. The semiconductor device of claim 18 , wherein the upper crystal structure control layer is provided between the ferroelectric dielectric layer and the gate electrode and includes Si-doped TiN.