Infrastructure integrity checking

1. A device, comprising:

a first component having a data input and a data output including a first line and a second line;

an error correction code (ECC) generation circuit having an input coupled to the data input of the first component, the ECC generation circuit having an output;

a second component having a data input coupled to the output of the ECC generation circuit, the second component having a data output;

an ECC error detection circuit having a first data input including a first line and a second line, wherein the first line of the first data input of the ECC error detection circuit is coupled to the first line of the data output of the first component, and wherein the ECC error detection circuit further includes a second data input coupled to the data output of the second component; and

a logic gate including a first input coupled to the second line of the data output of the first component,

wherein the logic gate further includes an output coupled to the second line of the first data input of the ECC error detection circuit.

2. The device of claim 1 , further comprising a control signal comparator circuit having a first control input coupled to a control output of the first component and having a second control input coupled to a control output of the second component.

3. The device of claim 2 , wherein the control signal comparator circuit is configured to compare control bits from the control output of the first component to corresponding control bits from the control output of the second component.

4. The device of claim 3 , wherein the control signal comparator circuit is configured to assert an error signal responsive to a mismatch between the control bits from the control output of the first component to the corresponding control bits from the control output of the second component.

5. The device of claim 1 , wherein:

the ECC generation circuit is configured to generate ECC words based on data received on the input of the ECC generation circuit and provide the ECC words on the output of the ECC generation circuit;

the ECC words generated by the ECC generation circuit comprise a first set of ECC bits; and

the ECC error detection circuit is configured to calculate a second set of ECC bits based on data on the data output of the first component and to compare the second set of ECC bits to the first set of ECC bits contained in the ECC words provided on the output of the ECC generation circuit.

6. The device of claim 5 ,

wherein the second component is configured to provide the ECC words to the ECC error detection circuit, and

wherein the ECC error detection circuit is configured to compare the first set of ECC bits contained in the ECC words received from the second component to the second set of ECC bits.

7. The device of claim 1 ,

wherein the first component is configured to perform bus width conversion between the data input of the first component and the data output of the first component, and

wherein the second component is configured to perform bus width conversion between the data input of the second component and the data output of the second component.

8. The device of claim 1 , wherein the first component is configured to perform at least one of address decoding, arbitration, bus protocol conversion, or burst split.

9. The device of claim 1 , wherein the second component comprises a same instance of a circuit that comprises the first component.

10. The device of claim 1 ,

wherein the logic gate includes a second input configured to receive an error injection signal, and

wherein when the error injection signal is asserted to a first state, a bit of the second line of the first data input of the ECC error detection circuit is an opposite state as a corresponding bit of the second line of the data output of the first component.

11. The device of claim 10 , wherein the logic gate comprises an exclusive-OR gate.

12. A device, comprising:

a first component having a data input, a control output, and a data output;

an error correction code (ECC) generation circuit having an input coupled to the data input of the first component, the ECC generation circuit having an output;

a second component having a data input, a control output, and a data output, the data input of the second component is coupled to the output of the ECC generation circuit;

a control signal comparator circuit having a first control input coupled to the control output of the first component, a second control input coupled to the control output of the second component, a data input coupled to the data output of the first component, and a data output; and

an ECC error detection circuit having a first data input coupled to the data output of the control signal comparator circuit, and the ECC error detection circuit including a second data input coupled to the data output of the second component.

13. The device of claim 12 , wherein the control signal comparator circuit is configured to compare control bits from the control output of the first component to corresponding control bits from the control output of the second component.

14. The device of claim 12 , wherein:

the ECC generation circuit is configured to generate ECC words based on data received on the input of the ECC generation circuit and provide the ECC words on the output of the ECC generation circuit to the data input of the second component;

the ECC words generated by the ECC generation circuit comprise a first set of ECC bits; and

the ECC error detection circuit is configured to calculate a second set of ECC bits based on data on the data output of the first component and to compare the second set of ECC bits to first set of ECC bits contained in the ECC words received on the second data input from the data output of the second component.

15. The device of claim 12 , wherein the first component is configured to perform at least one of bus width conversion, address decoding, arbitration, bus protocol conversion, or burst split.

16. The device of claim 12 , wherein the second component comprises a same instance of a circuit that comprises the first component.

17. A system-on-chip (SoC), comprising:

a first component having a data input and a data output, the first component configured to perform a function of at least one of bus width conversion, address decoding, arbitration, bus protocol conversion, or burst splitting;

an error correction code (ECC) generation circuit having an input coupled to the data input of the first component, the ECC generation circuit having an output;

a second component having a data input coupled to the output of the ECC generation circuit, the second component having a data output, the second component configured to perform the at least one of bus width conversion, address deconding, arbitration, bus protocol conversion, or burst splitting; and

an ECC error detection circuit having a first data input coupled to the data output of the first component, and the ECC error detection circuit including a second data input coupled to the data output of the second component.

18. The SoC of claim 17 , further comprising a control signal comparator circuit having a first control input coupled to a control output of the first component and having a second control input coupled to a control output of the second component,

wherein the control signal comparator circuit is configured to compare control bits from the control output of the first component to corresponding control bits from the control output of the second component.

19. The SoC of claim 17 , wherein:

the ECC generation circuit is configured to generate ECC words based on data received on the input of the ECC generation circuit and provide the ECC words on the output of the ECC generation circuit;

the ECC words generated by the ECC generation circuit comprise a first set of ECC bits; and

the ECC error detection circuit is configured to calculate a second set of ECC bits based on data on the data output of the first component and to compare the second set of ECC bits to the first set of ECC bits contained in the ECC words provided on the output of the ECC generation circuit.

20. The SoC of claim 17 ,

wherein the first component includes first circuitry, and

wherein the second component includes second circuitry comprising a same instance of the first circuitry.

21. A device, comprising:

a first component including a data input and a data output;

an error correction code (ECC) generation circuit including an input coupled to the data input of the first component, wherein the ECC generation circuit further includes an output, wherein the ECC generation circuit is configured to generate ECC words based on data received on the input of the ECC generation circuit and provide the ECC words on the output of the ECC generation circuit, and wherein the ECC words generated by the ECC generation circuit comprise a first set of ECC bits;

a second component including a data input coupled to the output of the ECC generation circuit, wherein the second component further includes a data output; and

an ECC error detection circuit including a first data input coupled to the data output of the first component,

wherein the ECC error detection circuit further includes a second data input coupled to the data output of the second component, and

wherein the ECC error detection circuit is configured to calculate a second set of ECC bits based on data on the data output of the first component and to compare the second set of ECC bits to the first set of ECC bits contained in the ECC words provided on the output of the ECC generation circuit.

22. A device, comprising:

a first component including a data input and a data output, wherein the first component comprises first circuitry;

an error correction code (ECC) generation circuit including an input coupled to the data input of the first component, wherein the ECC generation circuit further includes an output;

a second component including a data input coupled to the output of the ECC generation circuit, wherein the second component further includes a data output, wherein the second component comprises second circuitry, and wherein the second circuitry comprises a same instance of the first circuitry; and

an ECC error detection circuit including a first data input coupled to the data output of the first component,

wherein the ECC error detection circuit further includes a second data input coupled to the data output of the second component.