Memory system
According to one embodiment, a memory system includes a nonvolatile memory and a controller electrically connected to the nonvolatile memory. The controller selects a write mode from a first mode in which data having N bits is written per one memory cell and a second mode in which data having M bits is written per one memory cell. N is equal to or larger than one. M is larger than N. The controller writes data into the nonvolatile memory in the selected write mode. The controller selects either the first mode or the second mode at least based on a total number of logical addresses mapped in a physical address space of the nonvolatile memory.
1. A memory system connectable to a host, the memory system comprising:
a nonvolatile memory including a plurality of memory cells; and
a controller configured to write data to the nonvolatile memory in either a first mode or a second mode, a number of bits of data written in a memory cell in the second mode being larger than a number of bits of data written in a memory cell in the first mode, wherein
the controller is further configured to:
determine a size of a first region of the nonvolatile memory for writing data in the first mode, based on a ratio of (A) a total number of logical addresses mapped to physical addresses of the nonvolatile memory to (B) an entire logical address space of the memory system;
write first data, which is received from the host, into the first region in the first mode;
determine that a size of an available area in the first region for writing data is smaller than a threshold;
in response to determining that the size of the available area in the first region is smaller than the threshold, determine to write the first data stored in the first region into a second region of the nonvolatile memory in the second mode; and
write the first data stored in the first region into the second region of the nonvolatile memory in the second mode.
2. The memory system according to claim 1 , wherein
the controller is configured to write the first data stored in the first region into the second region in response to the first region reaching its full capacity.
3. The memory system according to claim 1 , wherein
the controller is further configured to:
allocate a third region in the nonvolatile memory; and
write second data, which is received from the host, into the third region not in the second mode but in the first mode.
4. The memory system according to claim 1 , wherein
the ratio decreases in response to execution of an unmap command.
5. The memory system according to claim 1 , wherein
the first mode is a single-level-cell (SLC) mode and the second mode is a quad-level-cell (QLC) mode.
6. A method of controlling a nonvolatile memory in a memory system, the nonvolatile memory including a plurality of memory cells, the method comprising:
determining a size of a first region of the nonvolatile memory for writing data in a first mode, based on a ratio of (A) a total number of logical addresses mapped to physical addresses of the nonvolatile memory to (B) an entire logical address space of the memory system;
writing first data, which is received from a host, into the first region in the first mode;
determining that a size of an available area in the first region for writing data is smaller than a threshold;
in response to determining that the size of the available area in the first region is smaller than the threshold, determining to write the first data stored in the first region into a second region of the nonvolatile memory in a second mode, a number of bits of data written in a memory cell in the second mode being larger than a number of bits of data written in a memory cell in the first mode; and
writing the first data stored in the first region into the second region of the nonvolatile memory in the second mode.
7. The control method according to claim 6 , wherein
the writing of the first data stored in the first region into the second region is performed in response to the first region reaching its full capacity.
8. The method according to claim 6 , further comprising:
allocating a third region in the nonvolatile memory; and
writing second data, which is received from the host, into the third region not in the second mode but in the first mode.
9. The control method according to claim 6 , wherein
the ratio decreases in response to execution of an unmap command.
10. The method according to claim 6 , wherein
the first mode is a single-level-cell (SLC) mode and the second mode is a quad-level-cell (QLC) mode.