Interconnect structure for high power GaN module including a printed planar interconnect line and method for making the same
In described examples of a circuit module, a multilayer substrate has a conductive pad formed on a surface of the multilayer substrate. An integrated circuit (IC) die is bonded to the surface of the substrate in dead bug manner, such that a set of bond pads formed on a surface of the IC die are exposed. A planar interconnect line formed by printed ink couples the set of bond pads to the conductive pad.
1. A circuit module comprising:
a multilayer substrate having a first surface and an opposite second surface;
a first conductive pad formed within a first one of the layers of the multilayer substrate;
an integrated circuit (IC) die having a first surface and an opposite second surface, the IC die having a semiconductor device formed therein, the semiconductor device having a set of bond pads formed on the first surface of the IC die, the second surface of the IC die being bonded to the first surface of the multilayer substrate; and
a first printed ink planar interconnect line coupled to a subset of the set of bond pads and to the conductive pad.
2. The circuit module of claim 1 , wherein the printed ink includes copper particles.
3. The circuit module of claim 1 , wherein the printed ink includes silver or gold particles.
4. The circuit module of claim 1 , wherein a heat dispersing layer of the multilayer substrate forms the second surface of the multilayer substrate.
5. The circuit module of claim 1 , wherein the semiconductor device is a GaN FET.
6. The circuit module of claim 1 , further comprising:
a second IC die mounted to the first surface of the multilayer substrate;
at least one passive component coupled to the first surface of the multilayer substrate; and
encapsulation material covering the first surface of the multilayer substrate, the IC die, the second IC die, and the passive component.
7. The circuit module of claim 6 , further comprising a printed ink planar interconnect control line coupled between a terminal on the second IC and a terminal in the semiconductor device.
8. A circuit module comprising:
a multilayer substrate having a first surface and an opposite second surface;
a first conductive pad formed within a first one of the layers of the multilayer substrate;
a second conductive pad formed within a second one of the layers of the multilayer substrate;
an integrated circuit (IC) die having a first surface and an opposite second surface, the IC die having a semiconductor device formed therein, the semiconductor device having a set of bond pads formed on the first surface of the IC die, wherein the set of bond pads is a first set of bond pads and the semiconductor device has a second set of bond pads formed on the first surface of the IC die, the second surface of the IC die being bonded to the first surface of the multilayer substrate;
a first printed ink planar interconnect line coupled to the set of bond pads and to the conductive pad; and
a second printed ink planar interconnect line coupled to the second set of bond pads and to the second conductive pad.
9. A circuit module comprising:
a multilayer substrate having a first surface and an opposite second surface;
a first conductive pad formed within a first one of the layers of the multilayer substrate;
a second conductive pad formed within a second one of the layers of the multilayer substrate;
an integrated circuit (IC) die having a first surface and an opposite second surface, the IC die having a GaN FET semiconductor device formed therein, the GaN FET having a set of source bond pads, a set of drain bond pads, and a gate bond pad all formed on the first surface of the IC die, the second surface of the IC die being bonded to the first surface of the multilayer substrate;
a first printed ink planar interconnect line coupled to the set of source bond pads and to the first conductive pad; and
a second printed ink planar interconnect line coupled to the set of drain bond pads and to the second conductive pad.
10. The circuit module of claim 9 further comprising:
a second IC die mounted to the first surface of the multilayer substrate, the second IC having an output bond pad; and
a third printed ink planar interconnect line coupled between the output bond pad on the second IC and the gate bond pad on the GaN FET.
11. The circuit module of claim 9 , wherein the printed ink includes copper particles.
12. The circuit module of claim 9 , wherein the printed ink includes silver or gold particles.
13. The circuit module of claim 9 , wherein a heat dispersing layer of the multilayer substrate forms the second surface of the multilayer substrate.
14. A method for fabricating a module, the method comprising:
fabricating a multilayer substrate having an exposed surface;
patterning a first conductive layer of the multilayer substrate to form a conductive pad;
patterning a second conductive layer of the multilayer substrate to form a second conductive pad;
bonding an integrated circuit (IC) die to the exposed surface of the multilayer substrate such that a set of bond pads on the IC die face away from the exposed surface of the multilayer substrate;
printing a patterned layer of dielectric over the IC die and the conductive pad such that the set of bond pads and the conductive pad are exposed;
printing a patterned layer of conductive ink to form a first printed ink planar interconnect line to couple a portion of the set of bond pads to the conductive pad; and
wherein printing the patterned layer of conductive ink also forms a second printed ink planar interconnect line to couple a second portion of the set of bond pads to the second conductive pad.