Laterally-diffused metal-oxide semiconductor transistor and method therefor

1. A method comprising:

etching a trench in a semiconductor substrate, the trench having a first sidewall and a second sidewall;

forming a substantially vertical conductive spacer from a first conductive layer deposited in the trench, the conductive spacer proximate to the first sidewall;

depositing a dielectric material to substantially fill the trench, the dielectric material substantially surrounding the conductive spacer;

forming a drift region in the semiconductor substrate adjacent to the first sidewall and a first portion of the second sidewall, the drift region having a first conductivity type;

forming a drain region in the drift region, the drain region directly adjacent to a second portion of the second sidewall separate from and above the first portion of the second sidewall; and

forming a first gate region from a second conductive layer deposited over the semiconductor substrate, the first gate region overlapping a portion of the drift region and not overlapping the dielectric material.

2. The method of claim 1 , further comprising forming a second gate region from the second conductive layer, the second gate region formed over the dielectric material.

3. The method of claim 2 , further comprising forming a non-conductive layer over spanning adjacent portions of the drift region and the dielectric material between the first gate region and the second gate region, the non-conductive layer overlapping a portion of the first gate region.

4. The method of claim 1 , wherein the first conductive layer and the second conductive layer are each formed from a polysilicon material.

5. The method of claim 1 , further comprising forming a source region in the semiconductor substrate, the first gate region formed over the semiconductor substrate between the source region and the first sidewall.

6. The method of claim 5 , further comprising forming a body region having a second conductivity type in the semiconductor substrate adjacent to the drift region, the source region formed in the body region.

7. The method of claim 1 , further comprising forming a gate dielectric layer over the semiconductor substrate, the second conductive layer deposited on the gate dielectric layer.

8. A method comprising:

etching a trench in a semiconductor substrate, the trench having a first sidewall, a second sidewall, and a bottom surface;

depositing a dielectric layer on the first sidewall, the second sidewall, and the bottom surface of the trench with a conductive material to form a gate region;

depositing a first conductive layer on the dielectric layer;

selectively etching the first conductive layer to remove the first conductive layer proximate to the second sidewall and the bottom surface of the trench, a conductive spacer formed by the remaining conductive layer proximate to the first sidewall;

depositing a dielectric material to substantially fill the trench, the dielectric material substantially surrounding the conductive spacer;

forming a drift region in the semiconductor substrate adjacent to the first sidewall and a first portion of the second sidewall, the drift region having a first conductivity type;

forming a drain region in the drift region, the drain region directly adjacent to a second portion of the second sidewall separate from and above the first portion of the second sidewall; and

forming a first gate region from a second conductive layer deposited over the semiconductor substrate, the first gate region overlapping a portion of the drift region and not overlapping the dielectric material.

9. The method of claim 8 , further comprising:

forming a body region in the semiconductor substrate adjacent to the drift region, the body region having a second conductivity type; and

forming a source region in the body region, the first gate region formed over the semiconductor substrate between the source region and the first sidewall.

10. The method of claim 9 , further comprising:

forming a first contact conductively connected to the conductive spacer;

forming a second contact conductively connected to the first gate region;

forming a third contact conductively connected to the source region; and

interconnecting the first contact with the second contact or the third contact.

11. The method of claim 8 , wherein the first conductive layer and the second conductive layer are each formed from a polysilicon material.