Semiconductor memory device and erasing method of the semiconductor memory device

1. A semiconductor memory device comprising:

a plurality of word lines stacked between a source conductive pattern and a bit line;

at least two drain select lines disposed between the plurality of word lines and the bit line, the at least two drain select lines being spaced apart from each other in an extending direction of the bit line; and

an erase control line disposed between the at least two drain select lines and the plurality of word lines.

2. The semiconductor memory device of claim 1 , wherein the at least two drain select lines includes an odd-numbered drain select line and an even-numbered drain select line, which are spaced apart from each other at a same level.

3. The semiconductor memory device of claim 2 , further comprising:

an odd pillar group connected to the source conductive pattern and extending toward the bit line, the odd pillar group penetrating the odd-numbered drain select line; and

an even pillar group connected to the source conductive pattern and extending toward the bit line, the even pillar group penetrating the even-numbered drain select line,

wherein each of the plurality of word lines and the erase control line extends to surround the odd pillar group and the even pillar group.

4. The semiconductor memory device of claim 1 , further comprising:

channel structures connected to the source conductive pattern and extending to penetrate the plurality of word lines and the erase control line; and

drain-side channel structures connected to the channel structures and extending to penetrate the at least two drain select lines,

wherein a number of the drain-side channel structures penetrating one drain select line of the at least two drain select lines is smaller than that of the channel structures penetrating the erase control line.

5. The semiconductor memory device of claim 1 , further comprising:

a slit disposed between drain select lines adjacent to each other among the at least two drain select lines, the slit overlapping with the plurality of word lines and the erase control line; and

pillar structures extending from the source conductive pattern to penetrate the plurality of word lines, the erase control line, and the at least two drain select lines.

6. The semiconductor memory device of claim 5 , wherein the pillar structures are divided into at least two pillar groups respectively corresponding to the at least two drain select lines,

wherein the slit is disposed between pillar groups adjacent to each other among the at least two pillar groups.

7. The semiconductor memory device of claim 1 , wherein a lateral width of each of the at least two drain select lines is narrower than that of the plurality of word lines and the erase control line.

8. The semiconductor memory device of claim 1 , further comprising:

a source select line disposed between the plurality of word lines and the source conductive pattern; and

a dummy word line disposed in at least one of a first region between the plurality of word lines and the erase control line and a second region between the plurality of word lines and the source select line.

9. The semiconductor memory device of claim 8 , wherein each of the source select line and the dummy word line is formed to have a lateral width wider than that of each of the at least two drain select lines.

10. The semiconductor memory device of claim 1 , wherein each of the drain select lines is formed thicker than each of the plurality of word lines and the erase control line in a stack direction of the plurality of word lines.

11. The semiconductor memory device of claim 1 , further comprising a substrate disposed closer to the bit line than the source conductive pattern, the substrate including a peripheral circuit.

12. The semiconductor memory device of claim 1 , further comprising a substrate disposed closer to the source conductive pattern than the bit line, the substrate including a peripheral circuit.

13. A semiconductor memory device comprising:

a source conductive pattern;

a first channel structure and a second channel structure, which are connected to the source conductive pattern;

a first drain-side channel structure connected to the first channel structure;

a second drain-side channel structure connected to the second channel structure;

a first drain select line surrounding the first drain-side channel structure;

a second drain select line surrounding the second drain-side channel structure;

a word line disposed between the source conductive pattern and the first drain select line, the word line extending to surround the first channel structure and the second channel structure; and

an erase control line disposed between the word line and the first drain select line, the erase control line extending to surround the first channel structure and the second channel structure.

14. The semiconductor memory device of claim 13 , wherein each of the first drain-side channel structure and the second drain-side channel structure is formed to have a lateral width narrower than that of each of the first channel structure and the second channel structure.

15. The semiconductor memory device of claim 13 , wherein a distance between the first drain-side channel structure and the second drain-side channel structure is greater than that between the first channel structure and the second channel structure in a lateral direction parallel to a top surface of the source conductive pattern.

16. The semiconductor memory device of claim 13 , wherein each of the first channel structure and the second channel structure includes:

a core insulating layer;

a doped semiconductor layer on the core insulating layer; and

a channel layer extending along a sidewall of the core insulating layer and a sidewall of the doped semiconductor layer,

wherein the doped semiconductor layer extends to face a sidewall of the erase control line.

17. The semiconductor memory device of claim 13 , wherein each of the first drain-side channel structure and the second drain-side channel structure includes a doped semiconductor layer.

18. The semiconductor memory device of claim 13 , further comprising a source select line disposed between the word line and the source conductive pattern, the source select line extending to surround the first channel structure and the second channel structure.

19. The semiconductor memory device of claim 13 , wherein each of the first drain select line and the second drain select line is formed thicker than each of the word line and the erase control line in a direction perpendicular to a top surface of the source conductive pattern.

20. The semiconductor memory device of claim 13 , wherein each of the first drain select line and the second drain select line is formed to have a lateral width narrower than that of each of the word line and the erase control line.