Forksheet transistors with dielectric or conductive spine
Embodiments disclosed herein include forksheet transistor devices having a dielectric or a conductive spine. For example, an integrated circuit structure includes a dielectric spine. A first transistor device includes a first vertical stack of semiconductor channels spaced apart from a first edge of the dielectric spine. A second transistor device includes a second vertical stack of semiconductor channels spaced apart from a second edge of the dielectric spine. An N-type gate structure is on the first vertical stack of semiconductor channels, a portion of the N-type gate structure laterally between and in contact with the first edge of the dielectric spine and the first vertical stack of semiconductor channels. A P-type gate structure is on the second vertical stack of semiconductor channels, a portion of the P-type gate structure laterally between and in contact with the second edge of the dielectric spine and the second vertical stack of semiconductor channels.
1. An integrated circuit structure, comprising:
a dielectric spine;
a first transistor device comprising a first vertical stack of semiconductor channels spaced apart from a first edge of the dielectric spine;
a second transistor device comprising a second vertical stack of semiconductor channels spaced apart from a second edge of the dielectric spine;
an N-type gate structure on the first vertical stack of semiconductor channels, a portion of the N-type gate structure laterally between and in contact with the first edge of the dielectric spine and the semiconductor channels of the first vertical stack of semiconductor channels; and
a P-type gate structure on the second vertical stack of semiconductor channels, a portion of the P-type gate structure laterally between and in contact with the second edge of the dielectric spine and the semiconductor channels of the second vertical stack of semiconductor channels.
2. The integrated circuit structure of claim 1 , wherein the first and second vertical stacks of semiconductor channels are first and second stacks of nanoribbons or nanowires.
3. The integrated circuit structure of claim 1 , wherein a total number of semiconductor channels in the first vertical stack of semiconductor channels is the same as a total number of semiconductor channels in the second vertical stack of semiconductor channels.
4. The integrated circuit structure of claim 1 , wherein a total number of semiconductor channels in the first vertical stack of semiconductor channels is different than a total number of semiconductor channels in the second vertical stack of semiconductor channels.
5. An integrated circuit structure, comprising:
a conductive spine;
first and second dielectric spacers along first and second edges of the conductive spine, respectively;
a first transistor device comprising a first vertical stack of semiconductor channels adjacent to the first dielectric spacer along the first edge of the conductive spine; and
a second transistor device comprising a second vertical stack of semiconductor channels adjacent to the second dielectric spacer along the second edge of the conductive spine.
6. The integrated circuit structure of claim 5 , wherein the first transistor device is a P-type device, and the second transistor device is an N-type device.
7. The integrated circuit structure of claim 5 , wherein the first and second vertical stacks of semiconductor channels are first and second stacks of nanoribbons or nanowires.
8. The integrated circuit structure of claim 5 , wherein a total number of semiconductor channels in the first vertical stack of semiconductor channels is the same as a total number of semiconductor channels in the second vertical stack of semiconductor channels.
9. The integrated circuit structure of claim 5 , wherein a total number of semiconductor channels in the first vertical stack of semiconductor channels is different than a total number of semiconductor channels in the second vertical stack of semiconductor channels.
10. The integrated circuit structure of claim 5 , further comprising:
a first gate structure on the first vertical stack of semiconductor channels, the first gate structure comprising a first gate electrode and a first gate dielectric; and
a second gate structure on the second vertical stack of semiconductor channels, the second gate structure comprising a second gate electrode and a second gate dielectric.
11. A computing device, comprising:
a board; and
a component coupled to the board, the component including an integrated circuit structure, comprising:
a dielectric spine;
a first transistor device comprising a first vertical stack of semiconductor channels spaced apart from a first edge of the dielectric spine;
a second transistor device comprising a second vertical stack of semiconductor channels spaced apart from a second edge of the dielectric spine;
an N-type gate structure on the first vertical stack of semiconductor channels, a portion of the N-type gate structure laterally between and in contact with the first edge of the dielectric spine and the semiconductor channels of the first vertical stack of semiconductor channels; and
a P-type gate structure on the second vertical stack of semiconductor channels, a portion of the P-type gate structure laterally between and in contact with the second edge of the dielectric spine and the semiconductor channels of the second vertical stack of semiconductor channels.
12. The computing device of claim 11 , further comprising:
a memory coupled to the board.
13. The computing device of claim 11 , further comprising:
a communication chip coupled to the board.
14. The computing device of claim 11 , further comprising:
a camera coupled to the board.
15. The computing device of claim 11 , wherein the component is a packaged integrated circuit die.
16. A computing device, comprising:
a board; and
a component coupled to the board, the component including an integrated circuit structure, comprising:
a conductive spine;
first and second dielectric spacers along first and second edges of the conductive spine, respectively;
a first transistor device comprising a first vertical stack of semiconductor channels adjacent to the first dielectric spacer along the first edge of the conductive spine; and
a second transistor device comprising a second vertical stack of semiconductor channels adjacent to the second dielectric spacer along the second edge of the conductive spine.
17. The computing device of claim 16 , further comprising:
a memory coupled to the board.
18. The computing device of claim 16 , further comprising:
a communication chip coupled to the board.
19. The computing device of claim 16 , further comprising:
a camera coupled to the board.
20. The computing device of claim 16 , wherein the component is a packaged integrated circuit die.