Memory device including interface circuit and method of operating the same

1. A memory system comprising:

a memory controller configured to exchange data according to a first clock, the data including one or more of read data and write data; and

a memory device including a plurality of non-volatile memories and an interface circuit connected to the memory controller and the plurality of non-volatile memories, the interface circuit configured to,

divide the first clock into a second clock based on a number of the plurality of non-volatile memories,

exchange the data with the plurality of non-volatile memories according to the second clock,

receive data strobe signals from the plurality of non-volatile memories, and

detect a skew based on a difference between times when the data strobe signals are received from the plurality of non-volatile memories.

2. The memory system of claim 1 , wherein the interface circuit comprises:

a deserializer configured to receive the write data from the memory controller, divide the first clock into the second clock based on the number of the plurality of non-volatile memories, divide the write data to generate divided write data, and to transmit the divided write data to respective ones of the plurality of non-volatile memories based on the second clock; and

a serializer configured to receive divided read data from the plurality of non-volatile memories based on the second clock, buffer the divided read data, generate the read data based on the divided read data, and transmit the read data to the memory controller based on the first clock, wherein

the interface circuit is configured to improve an operating frequency of the memory system by dividing the write data into the divided write data via the deserializer, and to reduce loading between the memory controller and the plurality of non-volatile memories by buffering the divided read data output from each of the plurality of non-volatile memories in the serializer.

3. The memory system of claim 2 , wherein the serializer comprises:

a plurality of buffer registers connected to respective ones of the plurality of non-volatile memories, the plurality of buffer registers configured to buffer the divided read data received from the respective ones of the plurality of non-volatile memories; and

a combiner configured to generate the read data from the divided read data.

4. The memory system of claim 3 , wherein the interface circuit is further configured to determine, based on the skew, a delay time associated with the divided read data such that the divided read data buffered in different ones of the plurality of buffer registers correspond to each other.

5. The memory system of claim 4 , wherein the interface circuit is further configured to variably determine a margin based on memory sizes of the plurality of buffer registers.

6. The memory system of claim 5 , wherein the interface circuit is configured to determine the delay time based on the margin and a largest delay among the plurality of non-volatile memories.

7. The memory system of claim 3 , wherein the interface circuit is configured to determine, based on a set maximum delay, a delay time associated with the divided read data such that the divided read data buffered in different ones of the plurality of buffer registers correspond to each other.

8. The memory system of claim 7 , wherein the set maximum delay corresponds to a data access time (tDQSRE) parameter.

9. The memory system of claim 1 ,

wherein the plurality of non-volatile memories are one of NAND flash memory, vertical NAND flash memory, a vertical NAND flash based on a cell-on-peri (CoP) structure, and a vertical NAND flash memory having a stacked structure including 100 or more layers,

wherein a frequency of the first clock corresponds to a maximum operating frequency of the plurality of non-volatile memory devices, the maximum operating frequency being greater than or equal to 1 GHz, and

wherein a frequency of the second clock is 1/N times the frequency of the first clock, N being one of (i) a number of NAND flash memories or (ii) a multiple of 8 thereof, when a number of input/output structures in a single NAND flash memory is the multiple of 8.

10. An interface circuit device comprising:

a divider configured to divide a first clock received from a memory controller into a second clock, and to transmit the second clock to a first non-volatile memory and a second non-volatile memory;

a serializer including,

a first buffer register connected to the first non-volatile memory,

a second buffer register connected to the second non-volatile memory, and

a combiner configured to receive read data from each of the first buffer register and the second buffer register based on the first clock, and to output the read data to the memory controller; and

a time-to-digital converter (TDC) configured to delay the first buffer register and the second buffer register by,

performing a toggle operation from a time when the first clock is received from the memory controller,

receiving a first data strobe signal output by the first non-volatile memory according to the second clock, and

identifying that both the first buffer register and the second buffer register store data by halting the toggle operation in response to receiving a second data strobe signal output by the second non-volatile memory according to the second clock, wherein

the interface circuit device is configured to reduce loading between the memory controller and the first and second non-volatile memories by buffering the data output from the first and second non-volatile memories in the serializer.

11. The interface circuit device of claim 10 , wherein the interface circuit device is configured to increase the delay by a margin based on memory sizes of the first buffer register and the second buffer register.

12. The interface circuit device of claim 11 , wherein a length of the margin is reciprocal to the memory sizes of the first buffer register and the second buffer register.

13. The interface circuit device of claim 10 , wherein a frequency of the second clock is half a frequency of the first clock.

14. The interface circuit device of claim 10 , wherein the interface circuit device is configured determine, based on a set maximum delay, a delay time associated with the first buffer register and the second buffer register outputting data.

15. The interface circuit device of claim 14 , wherein the set maximum delay corresponds to a data access time (tDQSRE) parameter.

16. The interface circuit device of claim 10 ,

wherein the first non-volatile memory and the second non-volatile memory are one of NAND flash memory, vertical NAND flash memory, vertical NAND flash based on a cell-on peri (CoP) structure, and vertical NAND flash memory having a stacked structure including 100 or more layers, and

wherein a frequency of the first clock corresponds to a maximum operating frequency of the first non-volatile memory and the second non-volatile memory, and the maximum operating frequency being greater than or equal to 1 GHz.