Fabrication of gate-all-around integrated circuit structures having additive metal gates
Gate-all-around integrated circuit structures having additive metal gates are described. For example, an integrated circuit structure includes a first vertical arrangement of horizontal nanowires, and a second vertical arrangement of horizontal nanowires. A first gate stack is over the first vertical arrangement of horizontal nanowires, the first gate stack having a P-type conductive layer with a first portion surrounding the nanowires of the first vertical arrangement of horizontal nanowires and a second portion extending laterally beside and spaced apart from the first portion. A second gate stack is over the second vertical arrangement of horizontal nanowires, the second gate stack having an N-type conductive layer with a first portion surrounding the nanowires of the second vertical arrangement of horizontal nanowires and a second portion adjacent to and in contact with the second portion of the P-type conductive layer.
1. An integrated circuit structure, comprising:
a first vertical arrangement of horizontal nanowires;
a second vertical arrangement of horizontal nanowires;
a first gate stack over the first vertical arrangement of horizontal nanowires, the first gate stack having a P-type conductive layer with a first portion surrounding the nanowires of the first vertical arrangement of horizontal nanowires and a second portion extending laterally beside and spaced apart from the first portion, wherein the second portion of the P-type conductive layer is laterally between the first vertical arrangement of horizontal nanowires and the second vertical arrangement of horizontal nanowires, the second portion of the P-type conductive layer having a first sidewall and a second sidewall laterally opposite to the first sidewall, wherein the first sidewall and the second sidewall are vertical sidewalls of a same continuous portion of the P-type conductive layer, and wherein the second portion of the P-type conductive layer has an uppermost surface above an uppermost surface of one or more of the nanowires of the first vertical arrangement of horizontal nanowires or the second vertical arrangement of horizontal nanowires; and
a second gate stack over the second vertical arrangement of horizontal nanowires, the second gate stack having an N-type conductive layer with a first portion surrounding the nanowires of the second vertical arrangement of horizontal nanowires and a second portion adjacent to and in contact with the first sidewall and the second sidewall of the second portion of the P-type conductive layer.
2. The integrated circuit structure of claim 1 , wherein the first portion of the P-type conductive layer does not include erosion features.
3. The integrated circuit structure of claim 1 , further comprising:
a first pair of epitaxial source or drain structures at first and second ends of the first vertical arrangement of horizontal nanowires; and
a second pair of epitaxial source or drain structures at first and second ends of the second vertical arrangement of horizontal nanowires.
4. The integrated circuit structure of claim 3 , further comprising:
a first pair of conductive contacts on the first pair of epitaxial source or drain structures; and
a second pair of conductive contacts on the second pair of epitaxial source or drain structures.
5. The integrated circuit structure of claim 3 , wherein the first and second pairs of epitaxial source or drain structures are first and second pairs of non-discrete epitaxial source or drain structures.
6. The integrated circuit structure of claim 3 , wherein the first and second pairs of epitaxial source or drain structures are first and second pairs of discrete epitaxial source or drain structures.
7. An integrated circuit structure, comprising:
a first vertical arrangement of horizontal nanowires;
a second vertical arrangement of horizontal nanowires;
a first gate stack over the first vertical arrangement of horizontal nanowires, the first gate stack having an N-type conductive layer with a first portion surrounding the nanowires of the first vertical arrangement of horizontal nanowires and a second portion extending laterally beside and spaced apart from the first portion, wherein the second portion of the N-type conductive layer is laterally between the first vertical arrangement of horizontal nanowires and the second vertical arrangement of horizontal nanowires, the second portion of the N-type conductive layer having a first sidewall and a second sidewall laterally opposite to the first sidewall, wherein the first sidewall and the second sidewall are vertical sidewalls of a same continuous portion of the N-type conductive layer, and wherein the second portion of the N-type conductive layer has an uppermost surface above an uppermost surface of one or more of the nanowires of the first vertical arrangement of horizontal nanowires or the second vertical arrangement of horizontal nanowires; and
a second gate stack over the second vertical arrangement of horizontal nanowires, the second gate stack having a P-type conductive layer with a first portion surrounding the nanowires of the second vertical arrangement of horizontal nanowires and a second portion adjacent to and in contact with the first sidewall and the second sidewall of the second portion of the N-type conductive layer.
8. The integrated circuit structure of claim 7 , wherein the first portion of the P-type conductive layer does not include erosion features.
9. The integrated circuit structure of claim 7 , further comprising:
a first pair of epitaxial source or drain structures at first and second ends of the first vertical arrangement of horizontal nanowires; and
a second pair of epitaxial source or drain structures at first and second ends of the second vertical arrangement of horizontal nanowires.
10. The integrated circuit structure of claim 9 , further comprising:
a first pair of conductive contacts on the first pair of epitaxial source or drain structures; and
a second pair of conductive contacts on the second pair of epitaxial source or drain structures.
11. The integrated circuit structure of claim 9 , wherein the first and second pairs of epitaxial source or drain structures are first and second pairs of non-discrete epitaxial source or drain structures.
12. The integrated circuit structure of claim 9 , wherein the first and second pairs of epitaxial source or drain structures are first and second pairs of discrete epitaxial source or drain structures.
13. A computing device, comprising:
a board; and
a component coupled to the board, the component including an integrated circuit structure, comprising:
a first vertical arrangement of horizontal nanowires;
a second vertical arrangement of horizontal nanowires;
a first gate stack over the first vertical arrangement of horizontal nanowires, the first gate stack having a P-type conductive layer with a first portion surrounding the nanowires of the first vertical arrangement of horizontal nanowires and a second portion extending laterally beside and spaced apart from the first portion, wherein the second portion of the P-type conductive layer is laterally between the first vertical arrangement of horizontal nanowires and the second vertical arrangement of horizontal nanowires, the second portion of the P-type conductive layer having a first sidewall and a second sidewall laterally opposite to the first sidewall, wherein the first sidewall and the second sidewall are vertical sidewalls of a same continuous portion of the P-type conductive layer, and wherein the second portion of the P-type conductive layer has an uppermost surface above an uppermost surface of one or more of the nanowires of the first vertical arrangement of horizontal nanowires or the second vertical arrangement of horizontal nanowires; and
a second gate stack over the second vertical arrangement of horizontal nanowires, the second gate stack having an N-type conductive layer with a first portion surrounding the nanowires of the second vertical arrangement of horizontal nanowires and a second portion adjacent to and in contact with the first sidewall and the second sidewall of the second portion of the P-type conductive layer.
14. The computing device of claim 13 , further comprising:
a memory coupled to the board.
15. The computing device of claim 13 , further comprising:
a communication chip coupled to the board.
16. The computing device of claim 13 , wherein the component is a packaged integrated circuit die.
17. The computing device of claim 13 , wherein the component is selected from the group consisting of a processor, a communications chip, and a digital signal processor.
18. A computing device, comprising:
a board; and
a component coupled to the board, the component including an integrated circuit structure, comprising:
a first vertical arrangement of horizontal nanowires;
a second vertical arrangement of horizontal nanowires;
a first gate stack over the first vertical arrangement of horizontal nanowires, the first gate stack having an N-type conductive layer with a first portion surrounding the nanowires of the first vertical arrangement of horizontal nanowires and a second portion extending laterally beside and spaced apart from the first portion, wherein the second portion of the N-type conductive layer is laterally between the first vertical arrangement of horizontal nanowires and the second vertical arrangement of horizontal nanowires, the second portion of the N-type conductive layer having a first sidewall and a second sidewall laterally opposite to the first sidewall, wherein the first sidewall and the second sidewall are vertical sidewalls of a same continuous portion of the N-type conductive layer, and wherein the second portion of the N-type conductive layer has an uppermost surface above an uppermost surface of one or more of the nanowires of the first vertical arrangement of horizontal nanowires or the second vertical arrangement of horizontal nanowires; and
a second gate stack over the second vertical arrangement of horizontal nanowires, the second gate stack having a P-type conductive layer with a first portion surrounding the nanowires of the second vertical arrangement of horizontal nanowires and a second portion adjacent to and in contact with the first sidewall and the second sidewall of the second portion of the N-type conductive layer.
19. The computing device of claim 18 , further comprising:
a memory coupled to the board.
20. The computing device of claim 18 , further comprising:
a communication chip coupled to the board.
21. The computing device of claim 18 , wherein the component is a packaged integrated circuit die.
22. The computing device of claim 18 , wherein the component is selected from the group consisting of a processor, a communications chip, and a digital signal processor.