IP Library › Granted Patent US 12,119,317
Granted Patent B2
US 12,119,317 · App. 17/032,469 · Granted Oct 15, 2024

Singulation of microelectronic components with direct bonding interfaces

Inventors: Bhaskar Jyoti Krishnatreya (Hillsboro, OR); Nagatoshi Tsunoda (Tsukuba, JP); Shawna M. Liff (Scottsdale, AZ); Sairam Agraharam (Chandler, AZ)
Assignee: Intel Corporation
H01L24/08H01L21/4853H01L21/4857H01L21/565H01L23/3128H01L23/367H01L23/5383H01L23/5386H01L24/05H01L24/80H01L25/0652H01L25/50H01L2224/05147H01L2224/08145H01L2224/0823H01L2224/80895H01L2224/80896H01L2225/06541H01L2225/06586
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Quick Facts
Patent No.
US 12,119,317
App. No.
17/032,469
Granted
Oct 15, 2024
Kind
B2
Abstract

Disclosed herein are structures and techniques related to singulation of microelectronic components with direct bonding interfaces. For example, in some embodiments, a microelectronic component may include: a surface, wherein conductive contacts are at the surface; a trench at a perimeter of the surface; and a burr in the trench.

Claims (24)

1. A microelectronic assembly, comprising:

a first microelectronic component having a face having a first direct bonding interface, wherein the first microelectronic component has a trench at a perimeter of the face and having a depth;

a burr in the trench having a height that is less than the depth of the trench; and

a second microelectronic component having a second direct bonding interface, wherein the first direct bonding interface is direct bonded to the second direct bonding interface.

2. The microelectronic assembly of claim 1 , wherein the first direct bonding interface includes conductive contacts.

3. The microelectronic assembly of claim 2 , wherein a pitch of the conductive contacts is less than 20 microns.

4. The microelectronic assembly of claim 2 , wherein the conductive contacts include copper.

5. The microelectronic assembly of claim 2 , wherein the first direct bonding interface includes a dielectric material between adjacent ones of the conductive contacts.

6. The microelectronic assembly of claim 5 , wherein the dielectric material includes an inorganic dielectric material.

7. The microelectronic assembly of claim 1 , wherein the face is a first face, the trench is a first trench, the second direct bonding interface is at a second face of the second microelectronic component, and the second microelectronic component has a second trench at a perimeter of the second face.

8. The microelectronic assembly of claim 7 , wherein the second microelectronic component includes a burr in the second trench.

9. A system, comprising:

a circuit board; and

a microelectronic assembly, communicatively coupled to the circuit board, wherein the microelectronic assembly includes a face of a first microelectronic component direct bonded to a face of a second microelectronic component, and the face of the first microelectronic component includes a trench at its edges, wherein the trench has a depth and comprises a burr having a height that is less than the depth of the trench.

10. The system of claim 9 , wherein the system further includes a display communicatively coupled to the circuit board.

11. The microelectronic assembly of claim 1 , wherein the trench extends into a metallization stack of the first microelectronic component.

12. The microelectronic assembly of claim 1 , wherein the trench extends into a substrate of the first microelectronic component.

13. The microelectronic assembly of claim 12 , wherein the substrate includes a semiconductor material.

14. The microelectronic assembly of claim 1 , wherein the burr is at an edge of the trench.

15. The microelectronic assembly of claim 1 , wherein the burr has a height greater than 300 nanometers.

16. The microelectronic assembly of claim 1 , wherein the burr includes material of a substrate of the first microelectronic component.

17. The microelectronic assembly of claim 1 , wherein the first microelectronic component includes a substrate, and side surfaces of the substrate are convex, concave, or angled.

18. The microelectronic assembly of claim 1 , wherein the first microelectronic component includes a substrate, and side surfaces of the substrate are jagged.

19. The microelectronic assembly of claim 1 , wherein corners of the first microelectronic component are rounded.

Assignments (2)
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Jul 20, 2021
From: KRISHNATREYA, BHASKAR JYOTI; TSUNODA, NAGATOSHI; LIFF, SHAWNA M.; AGRAHARAM, SAIRAM
To: INTEL CORPORATION
Reel/Frame 056910/0225 →
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Sep 25, 2020
From: KRISHNATREYA, BHASKAR JYOTI; TSUNODA, NAGATOSHI; LIFF, SHAWNA M.; AGRAHARAM, SAIRAM
To: INTEL CORPORATION
Reel/Frame 053890/0922 →
Continuity (1)
Related Publication 20220102305A1 · Mar 31, 2022