Method for PRP/SGL handling for out-of-order NVME controllers
Read latency for a read operation to a host implementing a PRP/SGL buffer is reduced by generating an address table representing the linked-list structure defining the PRP/SGL buffer. The address table may be generated concurrently with reading of data referenced by the read command from a NAND storage device. A block table for tracking status of LBAs referenced by IO commands may include a reference to the address table which is used to transfer LBAs to host memory as soon as the address table is complete and a block of data referenced by an LBA has been read from the NAND storage device.
1. A method comprising:
receiving, by a storage controller coupled to a storage device, a read command referencing a data block; and
performing in parallel:
(a) generating a data structure representing a linked list of buffer locations within a host memory corresponding to the data block, wherein (a) further comprises:
generating an address table in which each entry of the address table includes a buffer location from the linked list and a length of the buffer location from the linked list, and a reference to another entry in the address table for each entry other than a last entry in the address table
adding an entry referencing the data block in a block table; and
adding a reference to the address table to the entry referencing the data block, wherein the entry referencing the data block in the block table further includes a reference to another entry in the block table;
(b) reading the data block from the storage device;
identifying a plurality of buffer locations corresponding to the data block from the address table; and
(c) writing the data block to the plurality of buffer locations, wherein the data block is one of a plurality of data blocks and (c) is performed for the plurality of data blocks in an order that does not correspond to an order of the buffer locations in the linked list, wherein the entry referencing the data block in the block table further includes a data ready flag and an address ready flag; and
wherein the method further comprises:
setting the address ready flag when (a) is complete;
setting the data ready flag when (b) is complete; and
performing (c) only when the address ready flag and data ready flag are set.
2. The method of claim 1 , wherein (a) completes before (b) completes.
3. The method of claim 1 , wherein the linked list of buffer locations includes a scatter-gather list (SGL) according to the non-volatile memory express (NVMe) specification.
4. The method of claim 1 , wherein the storage device is a NAND storage device.
5. A controller coupled to a storage device and programmed to:
receive a read command referencing a data block; and
perform in parallel:
(a) generate a data structure representing a linked list of buffer locations within a host memory corresponding to the data block; and
(b) read the data block from the storage device, wherein the controller is further programmed to perform (a) by:
generating an address table in which each entry of the address table includes a buffer location from the linked list and a length of the buffer location from the linked list, and a reference to another entry in the address table for each entry other than a last entry in the address table;
wherein the controller is further programmed to perform (a) by:
adding an entry referencing the data block in a block table; and
adding a reference to the address table to the entry referencing the data block;
wherein the entry referencing the data block in the block table further includes a reference to another entry in the block table;
wherein the controller is further programmed to:
identify a plurality of buffer locations corresponding to the data block from the address table; and
(c) write the data block to the plurality of buffer locations, wherein the data block is one of a plurality of data blocks referenced by the read command and the controller is further programmed to perform (c) for the plurality of data blocks in an order that does not correspond to an order of the buffer locations in the linked list;
wherein the entry referencing the data block in the block table further includes a data ready flag and an address ready flag; and
wherein the controller is further programmed to:
set the address ready flag when (a) is complete;
set the data ready flag when (b) is complete; and
perform (c) only when the address ready flag and data ready flag are set.
6. The controller of claim 5 , wherein the controller is programmed to complete (a) before completing (b).
7. The controller of claim 5 , wherein the linked list of buffer locations includes a scatter-gather list (SGL) according to the non-volatile memory express (NVMe) specification.
8. The controller of claim 5 , wherein the storage device is a NAND storage device.