Gate spacing in integrated circuit structures
Discussed herein is gate spacing in integrated circuit (IC) structures, as well as related methods and components. For example, in some embodiments, an IC structure may include: a first gate metal having a longitudinal axis; a second gate metal, wherein the longitudinal axis of the first gate metal is aligned with a longitudinal axis of the second gate metal; a first gate contact above the first gate metal; a second gate contact above the second gate metal; and an unordered region having an unordered lamellar pattern, wherein the unordered region is coplanar with the first gate contact and the second gate contact.
1. An integrated circuit (IC) structure, comprising:
a first gate metal having a longitudinal axis;
a second gate metal, wherein the longitudinal axis of the first gate metal is aligned with a longitudinal axis of the second gate metal;
a first gate contact above the first gate metal;
a second gate contact above the second gate metal; and
an unordered region having an unordered lamellar pattern, wherein the unordered region is coplanar with the first gate contact and the second gate contact.
2. The IC structure of claim 1 , further comprising:
a dielectric material between the first gate contact and the second gate contact, wherein the dielectric material is in the unordered region.
3. The IC structure of claim 1 , further comprising:
a gate cut dielectric material between the first gate metal and the second gate metal.
4. The IC structure of claim 3 , wherein the gate cut dielectric material is at least partially coplanar with the unordered region.
5. The IC structure of claim 3 , wherein the gate cut dielectric material is in the unordered region.
6. The IC structure of claim 1 , wherein a distance between the first gate metal and the second gate metal is between 10 nanometers and 200 nanometers.
7. The IC structure of claim 1 , wherein the IC structure further includes:
an array of channel regions, including a first channel region and an adjacent second channel region, wherein axes of the first channel region and the second channel region are parallel and offset;
a first region proximate to the first channel region;
a second region proximate to the second channel region, wherein one of the first region and the second region is a source region of a transistor and another one of the first region and the second region is a drain region of the transistor; and
an insulating material region at least partially between the first region and the second region.
8. The IC structure of claim 1 , further comprising:
fin-shaped channel regions.
9. The IC structure of claim 1 , wherein the unordered region is under a guard ring of the IC structure.
10. The IC structure of claim 9 , wherein the first gate metal and the second gate metal are not under the guard ring.
11. The IC structure of claim 1 , wherein the unordered region is at a periphery of a memory array.
12. The IC structure of claim 11 , wherein the first gate metal and the second gate metal are not at the periphery of the memory array.
13. An integrated circuit (IC) structure, comprising:
a first gate contact having a longitudinal axis;
a second gate contact, wherein the longitudinal axis of the first gate contact is aligned with a longitudinal axis of the second gate contact; and
a region having an unordered lamellar pattern, wherein the region is coplanar with the first gate contact and the second gate contact.
14. The IC structure of claim 13 , further comprising:
a dielectric material between the first gate contact and the second gate contact, wherein the dielectric material is in the region.
15. The IC structure of claim 14 , wherein the dielectric material includes nitrogen, oxygen, or carbon.
16. The IC structure of claim 13 , further comprising:
a gate cut dielectric material between the first gate contact and the second gate contact.
17. An integrated circuit (IC) structure, comprising:
a first gate having a longitudinal axis;
a second gate, wherein the longitudinal axis of the first gate is aligned with a longitudinal axis of the second gate; and
a region having an unordered lamellar pattern, wherein the region is coplanar with or above the first gate and the second gate.
18. The IC structure of claim 17 , further comprising:
a dielectric material between the first gate and the second gate, wherein the dielectric material is in the region.
19. The IC structure of claim 17 , further comprising:
a gate cut dielectric material between the first gate and the second gate.
20. The IC structure of claim 19 , wherein the gate cut dielectric material is at least partially coplanar with the region.