Circuitry and methods for power efficient generation of length markers for a variable length instruction set
Systems, methods, and apparatuses for power efficient generation of length markers for a variable length instruction set are described. In one embodiment, a hardware processor core includes a decoder circuit to decode instructions into decoded instructions, an execution circuit to execute the decoded instructions, an instruction cache, an instruction length decoder circuit, a predecode cache comprising a predecode bit, for each section of multiple sections of instruction data, that indicates when that section is identified as an end boundary of a variable length instruction, an incomplete decode table comprising a bit, for each proper subset of sections of instruction data, that indicates when that proper subset of sections has one or more invalid predecode bits in the predecode cache; and a fetch circuit to, for an incoming address of instruction data, perform a lookup in the instruction cache and the incomplete decode table, and, when there is a hit in the instruction cache for the instruction data at the incoming address and a hit in the incomplete decode table that indicates a proper subset of sections of the instruction data for the incoming address has one or more invalid predecode bits in the predecode cache, causes the instruction length decoder circuit to generate one or more predecode bits for the proper subset of sections of the instruction data for the incoming address that has the one or more invalid predecode bits.
1. A hardware processor core comprising:
a decoder circuit to decode instructions into decoded instructions;
an execution circuit to execute the decoded instructions;
an instruction cache;
an instruction length decoder circuit;
a predecode cache comprising a predecode bit, for each section of multiple sections of instruction data, that indicates when that section is identified as a boundary of a variable length instruction;
storage for an incomplete decode table comprising a single bit, for each proper subset of the multiple sections of the instruction data, that indicates when that proper subset of the multiple sections has one or more invalid predecode bits in the predecode cache; and
a fetch circuit to, for an incoming address of the instruction data, perform a lookup in the instruction cache and the incomplete decode table, and, when there is a hit in the incomplete decode table that indicates a first proper subset of the multiple sections of the instruction data for the incoming address has the one or more invalid predecode bits in the predecode cache and a hit in the instruction cache for the instruction data at the incoming address, cause the instruction length decoder circuit to generate one or more predecode bits for the first proper subset of the multiple sections of the instruction data for the incoming address that has the one or more invalid predecode bits.
2. The hardware processor core of claim 1 , wherein the instruction length decoder circuit is enabled from a disabled state when there is the hit in the instruction cache and the hit in the incomplete decode table.
3. The hardware processor core of claim 1 , wherein, when there is the hit in the instruction cache and the hit in the incomplete decode table, the instruction length decoder circuit is to send the one or more predecode bits for the first proper subset of the multiple sections of the instruction data for the incoming address to the decoder circuit.
4. The hardware processor core of claim 1 , wherein, when there is the hit in the instruction cache and the hit in the incomplete decode table, the instruction length decoder circuit is to store the one or more predecode bits in the predecode cache and update one or more corresponding bits in the incomplete decode table as valid.
5. The hardware processor core of claim 1 , wherein, when there is a miss in the instruction cache for the instruction data at the incoming address, the fetch circuit causes:
a fetch of the instruction data from memory;
the instruction length decoder circuit to generate one or more predecode bits for the instruction data at the incoming address; and
an update of one or more corresponding bits in the incomplete decode table as valid.
6. The hardware processor core of claim 1 , wherein the decoder circuit comprises instruction length verification circuitry that updates a counter with a number of incorrect predecode bits from the predecode cache for decoded instructions, and when the counter exceeds a threshold, enables the instruction length decoder circuit from a disabled state.
7. The hardware processor core of claim 1 , further comprising disable logic circuitry to perform a comparison of predecode bits from the predecode cache to corresponding predecode bits generated by the instruction length decoder circuit, and disable the instruction length decoder circuit from an enabled state when the comparison indicates matches exceed a disengagement threshold number of matches.
8. The hardware processor core of claim 1 , wherein the fetch circuit is to, when there is a miss in the incomplete decode table that indicates the first proper subset of the multiple sections of the instruction data for the incoming address has one or more valid predecode bits in the predecode cache and a hit in the instruction cache for the instruction data at the incoming address, cause the one or more valid predecode bits for the first proper subset of the multiple sections of the instruction data for the incoming address from the predecode cache and corresponding instruction data from the instruction cache to be sent to the decoder circuit.
9. A method comprising:
receiving an incoming address of instruction data at a fetch circuit of a processor;
performing a lookup in an instruction cache of the processor for the instruction data at the incoming address in response to the receiving;
performing a lookup in an incomplete decode table of the processor for the instruction data at the incoming address in response to the receiving, the incomplete decode table comprising a single bit, for each proper subset of multiple sections of the instruction data, that indicates when that proper subset of the multiple sections has one or more invalid predecode bits in a predecode cache of the processor comprising a predecode bit, for each section of the multiple sections of the instruction data, that indicates when that section is identified as a boundary of a variable length instruction; and
generating, when there is a hit in the incomplete decode table that indicates a first proper subset of the multiple sections of the instruction data for the incoming address has the one or more invalid predecode bits in the predecode cache and a hit in the instruction cache for the instruction data at the incoming address, one or more predecode bits for the first proper subset of the multiple sections of the instruction data for the incoming address that has the one or more invalid predecode bits by an instruction length decoder circuit of the processor.
10. The method of claim 9 , further comprising enabling the instruction length decoder circuit from a disabled state when there is the hit in the instruction cache and the hit in the incomplete decode table.
11. The method of claim 9 , further comprising sending the one or more predecode bits for the first proper subset of the multiple sections of the instruction data for the incoming address from the instruction length decoder circuit to a decoder circuit when there is the hit in the instruction cache and the hit in the incomplete decode table.
12. The method of claim 9 , further comprising storing the one or more predecode bits from the instruction length decoder circuit into the predecode cache and updating one or more corresponding bits in the incomplete decode table as valid when there is the hit in the instruction cache and the hit in the incomplete decode table.
13. The method of claim 9 , further comprising, when there is a miss in the instruction cache for the instruction data at the incoming address, fetching the instruction data from memory by the fetch circuit, generating one or more predecode bits for the instruction data at the incoming address by the instruction length decoder circuit, and updating one or more corresponding bits in the incomplete decode table as valid.
14. The method of claim 9 , further comprising updating a counter with a number of incorrect predecode bits from the predecode cache for decoded instructions by instruction length verification circuitry of the processor, and enabling the instruction length decoder circuit from a disabled state when the counter exceeds a threshold.
15. The method of claim 9 , further comprising performing a comparison of predecode bits from the predecode cache to corresponding predecode bits generated by the instruction length decoder circuit, and disabling the instruction length decoder circuit from an enabled state when the comparison indicates matches exceed a disengagement threshold number of matches.
16. The method of claim 9 , wherein, when there is a miss in the incomplete decode table that indicates the first proper subset of the multiple sections of the instruction data for the incoming address has one or more valid predecode bits in the predecode cache and a hit in the instruction cache for the instruction data at the incoming address, sending the one or more valid predecode bits for the first proper subset of the multiple sections of the instruction data for the incoming address from the predecode cache and corresponding instruction data from the instruction cache to a decoder circuit.
17. An apparatus comprising:
an instruction cache;
an instruction length decoder circuit;
a predecode cache comprising a predecode bit, for each section of multiple sections of instruction data, that indicates when that section is identified as a boundary of a variable length instruction;
storage for an incomplete decode table comprising a single bit, for each proper subset of multiple sections of the instruction data, that indicates when that proper subset of the multiple sections has one or more invalid predecode bits in the predecode cache; and
a circuit to, for an incoming address of the instruction data, perform a lookup in the instruction cache and the incomplete decode table, and, when there is a hit in the incomplete decode table that indicates a first proper subset of the multiple sections of the instruction data for the incoming address has the one or more invalid predecode bits in the predecode cache and a hit in the instruction cache for the instruction data at the incoming address, cause the instruction length decoder circuit to generate one or more predecode bits for the first proper subset of the multiple sections of the instruction data for the incoming address that has the one or more invalid predecode bits.
18. The apparatus of claim 17 , wherein the instruction length decoder circuit is enabled from a disabled state when there is the hit in the instruction cache and the hit in the incomplete decode table.
19. The apparatus of claim 17 , wherein, when there is the hit in the instruction cache and the hit in the incomplete decode table, the instruction length decoder circuit is to send the one or more predecode bits for the first proper subset of the multiple sections of the instruction data for the incoming address to a decoder circuit that decodes instructions into decoded instructions for execution.
20. The apparatus of claim 17 , wherein, when there is the hit in the instruction cache and the hit in the incomplete decode table, the instruction length decoder circuit is to store the one or more predecode bits in the predecode cache and update one or more corresponding bits in the incomplete decode table as valid.
21. The apparatus of claim 17 , wherein, when there is a miss in the instruction cache for the instruction data at the incoming address, the circuit causes:
a fetch of the instruction data from memory;
the instruction length decoder circuit to generate one or more predecode bits for the instruction data at the incoming address; and
an update of one or more corresponding bits in the incomplete decode table as valid.
22. The apparatus of claim 17 , further comprising instruction length verification circuitry that updates a counter with a number of incorrect predecode bits from the predecode cache for decoded instructions, and when the counter exceeds a threshold, enables the instruction length decoder circuit from a disabled state.
23. The apparatus of claim 17 , wherein the circuit is to perform a comparison of predecode bits from the predecode cache to corresponding predecode bits generated by the instruction length decoder circuit, and disable the instruction length decoder circuit from an enabled state when the comparison indicates matches exceed a disengagement threshold number of matches.
24. The apparatus of claim 17 , wherein the circuit is to, when there is and a miss in the incomplete decode table that indicates the first proper subset of the multiple sections of the instruction data for the incoming address has one or more valid predecode bits in the predecode cache and a hit in the instruction cache for the instruction data at the incoming address, cause the one or more valid predecode bits for the first proper subset of the multiple sections of the instruction data for the incoming address from the predecode cache and corresponding instruction data from the instruction cache to be sent to a decoder circuit that decodes instructions into decoded instructions for execution.