Scalable multi-key memory encryption
Embodiments of apparatuses, methods, and systems for scalable multi-key memory encryption are disclosed. In an embodiment, an apparatus includes a core, an encryption unit, and key identification hardware. The core is to write data to and read data from memory regions, each to be identified by a corresponding address. The encryption unit to encrypt data to be written and decrypt data to be read. The key identification hardware is to use a portion of the corresponding address to look up a corresponding key identifier in a key information data structure. The corresponding key identifier is one multiple key identifiers. The corresponding key identifier is to identify which one of multiple encryption keys is to be used to encrypt and decrypt the data.
1. An apparatus comprising:
a core to write data to and read data from a plurality of memory regions, each of the plurality of memory regions to be identified by a corresponding address;
an encryption unit to encrypt data to be written and decrypt data to be read, wherein the encryption unit is to use a plurality of encryption keys;
key identification hardware to use a portion of the corresponding address to look up a corresponding key identifier in a key information data structure, wherein, the corresponding key identifier is one of a plurality of key identifiers, and the corresponding key identifier is to identify one of the plurality of encryption keys to be used to encrypt and decrypt the data; and
an instruction decoder to decode a first instruction to write to the key information data structure, wherein the first instruction is the only way for software to write to the key information data structure and is to write only to the key information structure;
wherein the key information data structure is to include a first indicator corresponding to the corresponding key identifier, the first indicator to indicate whether a memory location identified by the corresponding address is private, the first indicator to be compared to a second indicator provided with the corresponding address for the look up.
2. The apparatus of claim 1 , wherein the portion of the corresponding address is an address of one of the plurality of memory region to be protected by encryption with the one of the plurality of encryption keys identified by the corresponding key identifier.
3. The apparatus of claim 2 , wherein the one of the plurality of memory regions is a page.
4. The apparatus of claim 3 , wherein the portion of the corresponding address is a page frame number.
5. The apparatus of claim 4 , wherein the corresponding address is an address of a memory location within the page.
6. The apparatus of claim 5 , wherein the key information data structure is to include an entry per page, wherein each entry is to include a key identifier field.
7. The apparatus of claim 6 , wherein each entry is to include an indicator to indicate whether data to be stored at the corresponding address is private.
8. The apparatus of claim 6 , wherein each entry is to include an indicator to indicate that the entry is one of a group of entries in which the key identifier field is storing a first key identifier, wherein the first key identifier is the same for each entry.
9. The apparatus of claim 1 , wherein the key information data structure is to be stored in a system memory, further comprising a key information cache to cache entries from the key information data structure.
10. The apparatus of claim 1 , wherein the instruction decoder is also to decode a second instruction to read from the key information data structure, wherein the second instruction is the only way for software to read from the key information data structure and is to read only from the key information structure.
11. The apparatus of claim 10 , wherein the second instruction has a format including a first field for an opcode and a second field for an operand, wherein the operand is to specify at least one of the plurality of memory regions.
12. The apparatus of claim 11 , wherein execution of the decoded second instruction includes reading the corresponding key identifier from the key information data structure, wherein the corresponding key identifier corresponds to the at least one of the plurality of memory regions.
13. The apparatus of claim 1 , wherein the first instruction has a format including a first field for an opcode, a second field for a first operand, and a third field for a second operand, wherein the first operand is to specify at least one of the plurality of memory regions and the second operand is to specify the corresponding key identifier.
14. The apparatus of claim 13 , wherein execution of the decoded first instruction includes writing the corresponding key identifier to the key information data structure, wherein the corresponding key identifier corresponds to the at least one of the plurality of memory regions.
15. A method comprising:
requesting data to be written from a core to one of a plurality of memory regions, each of the plurality of memory regions to be identified by a corresponding address;
looking up, using a portion of the corresponding address and key identification hardware, a corresponding key identifier in a key information data structure, wherein the corresponding key identifier is one of a plurality of key identifiers, and the corresponding key identifier is to identify one of a plurality of encryption keys;
comparing a first indicator to a second indicator, the first indicator corresponding to the corresponding key identifier in the key information data structure to indicate whether a memory location identified by the corresponding address is private, the second indicator provided with the corresponding address for the looking up;
if the first indicator indicates the memory location is private and matches the second indicator, encrypting the data using the one of the plurality of encryption keys; and
if the first indicator indicates the memory location is private and matches the second indicator, writing the corresponding key identifier to the key information data structure using a first instruction, wherein the first instruction is the only way for software to write to the key information data structure and is to write only to the key information structure.
16. The method of claim 15 , further comprising reading the corresponding key identifier from the key information data structure using a second instruction, wherein the second instruction is the only way for software to read from the key information data structure and is to read only to the key information structure.
17. A system comprising:
a memory;
a core to write data to and read data from a plurality of memory regions, each of the plurality of memory regions to be identified by a corresponding address;
an encryption unit to encrypt data to be written and decrypt data to be read, wherein the encryption unit is to use a plurality of encryption keys;
key identification hardware to use a portion of the corresponding address to look up a corresponding key identifier in a key information data structure, wherein the corresponding key identifier is one of a plurality of key identifiers, and the corresponding key identifier is to identify one of the plurality of encryption keys to be used to encrypt and decrypt the data; and
an instruction decoder to decode a first instruction to write to the key information data structure, wherein the first instruction is the only way for software to write to the key information data structure and is to write only to the key information structure;
wherein the key information data structure is to include a first indicator corresponding to the corresponding key identifier, the first indicator to indicate whether a memory location identified by the corresponding address is private, the first indicator to be compared to a second indicator provided with the corresponding address for the look up.
18. The system of claim 17 , wherein the core is to access the memory through a plurality of memory channels and at least a portion of the key information data structure is to be copied for more than one of the plurality of memory channels.