Semiconductor device having via protective layer

1. A semiconductor device comprising:

a via passivation layer disposed on an inactive surface of a substrate;

a through-electrode vertically penetrating the substrate and the via passivation layer;

a concave portion formed in a top surface of the via passivation layer, the concave portion being adjacent to the through-electrode; and

a via protective layer horizontally overlapping the via passivation layer and the through-electrode and filling the concave portion,

wherein, in a horizontal cross-sectional view, the via protective layer has a band shape surrounding the through-electrode, and

wherein the via protective layer includes polyimide, polyhydroxystyrene, polybenzoxazole, or polyamide.

2. The semiconductor device of claim 1 , wherein a width of a top surface of the via protective layer is 10 μm or less.

3. The semiconductor device of claim 1 , wherein a depth from a top surface of the via protective layer to a lower end thereof is 0.3 μm or less.

4. The semiconductor device of claim 1 , wherein the via passivation layer includes a lower passivation layer and an upper passivation layer disposed on the lower passivation layer.

5. The semiconductor device of claim 4 ,

wherein the lower passivation layer includes a lower horizontal portion extending in a horizontal direction on the inactive surface and a lower vertical portion in contact with the through-electrode, and

wherein the upper passivation layer includes an upper horizontal portion extending in a horizontal direction on the lower horizontal portion and an upper vertical portion in contact with the lower vertical portion.

6. The semiconductor device of claim 5 ,

wherein, in a horizontal cross-sectional view, the lower vertical portion surrounds the through-electrode, and

wherein the upper vertical portion surrounds the lower vertical portion.

7. The semiconductor device of claim 5 , wherein, in a horizontal cross-sectional view, the upper horizontal portion surrounds the via protective layer.

8. The semiconductor device of claim 5 , wherein top surfaces of the through-electrode, the lower vertical portion, the upper vertical portion, the via protective layer, and the upper horizontal portion are coplanar with each other.

9. The semiconductor device of claim 5 , wherein the concave portion is formed in a corner between the upper horizontal portion and the upper vertical portion.

10. The semiconductor device of claim 1 , further comprising:

a conductive pad connected to the through-electrode on the via passivation layer,

wherein an outer diameter of the via protective layer is larger than a horizontal width of the conductive pad.

11. The semiconductor device of claim 1 , wherein, in a horizontal cross-sectional view, the via protective layer has a second width larger than a first width.

12. The semiconductor device of claim 1 , wherein, in a horizontal cross-sectional view, the via protective layer includes a plurality of protruding portions and a plurality of depressed portions.

13. A semiconductor device comprising:

a via passivation layer disposed on an inactive surface of a substrate;

a first through-electrode and a second through-electrode vertically penetrating the substrate and the via passivation layer, the second through-electrode having a horizontal width larger than a horizontal width of the first through-electrode;

a first concave portion and a second concave portion formed in a top surface of the via passivation layer, the first concave portion being adjacent to the first through-electrode and the second concave portion being adjacent to the second through-electrode;

a first via protective layer filling the first concave portion; and

a second via protective layer filling the second concave portion,

wherein, in a horizontal cross-sectional view, the first via protective layer and the second via protective layer have band shapes surrounding the first through-electrode and the second through-electrode, respectively.

14. The semiconductor device of claim 13 , wherein, in a horizontal cross-sectional view, an inner diameter of the second via protective layer is larger than an inner diameter of the first via protective layer.

15. The semiconductor device of claim 13 , wherein, in a horizontal cross-sectional view, a width of the second via protective layer is larger than a width of the first via protective layer.

16. The semiconductor device of claim 13 , wherein top surfaces of the via passivation layer, the first through-electrode, the second through-electrode, the first via protective layer, and the second via protective layer are coplanar with each other.

17. The semiconductor device of claim 13 , wherein the via passivation layer includes a lower passivation layer and an upper passivation layer disposed on the lower passivation layer.

18. The semiconductor device of claim 17 ,

wherein the lower passivation layer includes a lower horizontal portion extending in a horizontal direction on the inactive surface, a first lower vertical portion in contact with the first through-electrode, and a second lower vertical portion in contact with the second through-electrode, and

wherein the upper passivation layer includes an upper horizontal portion extending in the horizontal direction on the lower horizontal portion, a first upper vertical portion in contact with the first lower vertical portion, and a second upper vertical portion in contact with the second lower vertical portion.

19. A semiconductor device comprising:

a substrate including an inactive surface and an active surface opposite the inactive surface;

an interlayer insulating layer disposed below the active surface;

a wiring structure disposed below the interlayer insulating layer;

a lower passivation layer including a lower horizontal portion disposed on the inactive surface, a lower vertical portion connected to the lower horizontal portion, and a lower concave portion formed between the lower horizontal portion and the lower vertical portion;

an upper passivation layer disposed on the lower passivation layer, the upper passivation layer including an upper horizontal portion disposed on the lower horizontal portion, an upper vertical portion connected to the upper horizontal portion, and an upper concave portion formed between the upper horizontal portion and the upper vertical portion, the upper vertical portion being in contact with a side surface of the lower vertical portion;

a through-electrode vertically penetrating the substrate, the lower passivation layer, the upper passivation layer, and the interlayer insulating layer; and

a via protective layer horizontally overlapping the upper horizontal portion, the upper vertical portion, and the through-electrode and to fill the upper concave portion,

wherein, in a horizontal cross-sectional view, the via protective layer has a band shape surrounding the through-electrode.