Semiconductor device including memory cell and fin arrangements
A semiconductor device includes at least one memory cell and at least one logic cell. The at least one logic cell is disposed next to the at least one memory cell and includes a plurality of fins. The plurality of fins are separated into a plurality of fin groups for forming transistors. A distance between two adjacent groups of the plurality of fin groups is different from a distance between another two adjacent groups of the plurality of fin groups. A method is also disclosed herein.
1. A method of fabricating an integrated circuit (IC), comprising:
in a logic cell disposed next to a memory cell,
forming at least three fin groups that are separate from each other and extend along a first direction, within a cell height of the logic cell that is equal to a cell height of the memory cell in a layout view, for forming corresponding transistors in the integrated circuit;
forming a first fin in the at least three fin groups to be aligned with a first one of memory fins of the memory cell; and
forming a second fin in the at least three fin groups to be not aligned with each of the memory fins,
wherein the second fin is adjacent to the first fin.
2. The method of claim 1 , wherein
the at least three fin groups comprise a first fin group, a second fin group, and a third fin group,
the second fin group is disposed between the first fin group and the third fin group in a layout view, and
a distance, between a top edge of a third fin in the first fin group and a top edge of a fourth fin that is in the second fin group and adjacent to the third fin, is not an integral multiple of a fin pitch between each adjacent two of fin grids.
3. The method of claim 1 , further comprising:
in the logic cell,
forming a plurality of first conductive rails in a first conductive layer above the at least three fin groups, in the integrated circuit; and
forming a plurality of second conductive rails in the first conductive layer, wherein the plurality of second conductive rails are disposed between the plurality of first conductive rails in a layout view.
4. The method of claim 1 , wherein in a layout view,
a plurality of fins of the logic cell are separated from a plurality of memory fins of the memory cell formed in the integrated circuit, wherein the plurality of memory fins extend toward the plurality of fins, and
at least one of the plurality of fins is not aligned with the plurality of memory fins.
5. The method of claim 1 , further comprising:
forming a third fin, a fourth fin and a fifth fin in the at least three fin groups,
wherein the fifth fin, the third fin, the first fin, the second fin and the fourth fin are arranged in order,
a first distance between the fourth fin and the second fin is substantially equal to a second distance between the first fin and the third fin, and
a third distance between the first fin and the second fin is different from a fourth distance between the fifth fin and the third fin.
6. A method, comprising:
disposing at least one logic cell next to at least one memory cell;
separating a plurality of fins in the at least one logic cell into a plurality of fin groups for forming transistors; and
disposing the plurality of fins extending along a first direction in which a plurality of fin grids extend,
wherein a distance between two adjacent groups of the plurality of fin groups is different from a distance between another two adjacent groups of the plurality of fin groups, and
at least one of the plurality of fins is not aligned with the plurality of fin grids.
7. The method of claim 6 ,
wherein each adjacent two of the plurality of fin grids have a fin pitch therebetween.
8. The method of claim 6 , further comprising:
aligning at least one of the plurality of fins with at least one of memory fins of the at least one memory cell.
9. The method of claim 6 , further comprising:
disposing a plurality of memory fins in the at least one memory cell toward the plurality of fins; and
separating the plurality of memory fins from the plurality of fins,
wherein at least one of the plurality of memory fins is not aligned with the plurality of fins.
10. The method of claim 6 , further comprising:
forming respective transistors by a first fin group, a second fin group, and a third fin group of the plurality of fin groups; and
disposing the second fin group between the first fin group and the third fin group,
wherein at least one of a distance between the first fin group and the second fin group or a distance between the second fin group and the third fin group is not an integral multiple of a fin pitch.
11. The method of claim 6 , further comprising:
disposing a plurality of first conductive rails in a first conductive layer above the plurality of fins;
disposing a plurality of second conductive rails in the first conductive layer and disposed between the plurality of first conductive rails;
separating the plurality of first conductive rails from the plurality of fins in a layout view; and
partially overlapping at least one of the plurality of second conductive rails with the plurality of fins in the layout view.
12. A method, comprising:
abutting a logic cell having a cell height to a memory cell having the cell height;
disposing a plurality of first fins, a plurality of second fins and a plurality of third fins of the memory cell, the plurality of first fins, the plurality of second fins and the plurality of third fins extending along a first direction;
forming the plurality of second fins based on the cell height and a plurality of fin grids that extend along the first direction;
separating the plurality of first fins, the plurality of second fins and the plurality of third fins from each other; and
substantially aligning at least one of the plurality of second fins with at least one of the plurality of first fins,
wherein the at least one of the plurality of second fins is not aligned with the plurality of fin grids.
13. The method of claim 12 , further comprising:
separating the plurality of second fins into a plurality of fin groups for forming transistors,
wherein the plurality of fin groups comprise a first fin group and a second fin group that is adjacent to the first fin group,
a distance, between a top edge of a first fin in the first fin group and a top edge of a second fin that is in the second fin group and adjacent to the first fin, is not an integral multiple of a fin pitch, and
each adjacent two of the plurality of fin grids have the fin pitch therebetween.
14. The method of claim 13 , further comprising:
forming a first transistor by the first fin group;
forming a second transistor by the second fin group;
forming a third transistor by a third fin group of the plurality of fin groups; and
disposing the second fin group between the first fin group and the third fin group,
wherein a distance between the first fin group and the second fin group is different from a distance between the second fin group and the third fin group.
15. The method of claim 12 , further comprising:
separating the plurality of second fins into a plurality of fin groups for forming respective transistors,
wherein a distance, between a top edge of a first fin in a first fin group of the plurality of fin groups and a top edge of a second fin that is adjacent to the first fin, in a second fin group of the plurality of fin groups, is larger than an integral multiple of a fin pitch, and
each adjacent two of the plurality of fin grids have the fin pitch therebetween.
16. The method of claim 12 , further comprising:
aligning at least one of the plurality of first fins with at least one of the plurality of fin grids in a layout view; and
separating the plurality of first fins from the plurality of second fins along the first direction,
wherein a distance between one of the plurality of first fins and one of the plurality of second fins is different from a distance between another one of the plurality of first fins and another one of the plurality of second fins.
17. The method of claim 12 , further comprising:
disposing a plurality of first conductive rails extending along the first direction in a first conductive layer above the plurality of first fins and the plurality of second fins;
disposing a plurality of second conductive rails extending along the first direction in the first conductive layer;
disposing the plurality of second conductive rails between the plurality of first conductive rails;
separating the plurality of first conductive rails from the plurality of second fins in a layout view; and
partially overlapping at least one of the plurality of second conductive rails with the plurality of second fins in the layout view.
18. The method of claim 17 , further comprising:
separating the plurality of second fins into a plurality of fin groups for forming transistors,
wherein a width of the plurality of first conductive rails is smaller than or equal to a distance between two adjacent fin groups of the plurality of fin groups, and
a width of one of the plurality of second conductive rails is larger than or equal to a width of one of the plurality of second fins.
19. The method of claim 17 , further comprising:
separating the plurality of second fins into a plurality of fin groups;
separating the plurality of second conductive rails into a plurality of rail groups;
separating adjacent two of the plurality of rail groups from each other by one of the plurality of first conductive rails; and
overlapping the plurality of fin groups and the plurality of rail groups in the layout view,
wherein a number of the plurality of fin groups is equal to a number of the plurality of rail groups.
20. The method of claim 17 , further comprising:
disposing a plurality of third conductive rails extending along the first direction in the first conductive layer; and
partially overlapping the plurality of third conductive rails with the plurality of first fins in the layout view,
wherein the plurality of third conductive rails are not aligned with at least one of the plurality of first conductive rails and the plurality of second conductive rails.