Semiconductor memory devices and methods of fabricating the same
Disclosed are semiconductor memory devices and methods of fabricating the same. The semiconductor memory devices may include a plurality of layers sequentially stacked on a substrate in a vertical direction, each of the plurality of layers including a bit line extending in a first direction and a semiconductor pattern extending from the bit line in a second direction traversing the first direction, a gate electrode extending through the plurality of layers and including a vertical portion extending through the semiconductor patterns and a first horizontal portion extending from the vertical portion and facing a first surface of one of the semiconductor patterns, and a data storing element electrically connected to the one of the semiconductor patterns. The data storing element includes a first electrode electrically connected to the one of the semiconductor patterns, a second electrode on the first electrode, and a dielectric layer between the first and second electrodes.
1. A semiconductor memory device comprising:
a plurality of layers sequentially stacked on a substrate in a vertical direction, each of the plurality of layers comprising a bit line extending in a first direction and a semiconductor pattern extending from the bit line in a second direction that traverses the first direction;
a gate electrode comprising a vertical portion extending through the semiconductor patterns and a first horizontal portion extending from the vertical portion and facing a first surface of one of the semiconductor patterns, wherein the vertical portion comprises portions that are in respective ones of the semiconductor patterns; and
a data storing element electrically connected to the one of the semiconductor patterns,
wherein the data storing element comprises:
a first electrode electrically connected to the one of the semiconductor patterns;
a second electrode on the first electrode; and
a dielectric layer between the first electrode and the second electrode.
2. The semiconductor memory device of claim 1 , wherein the gate electrode further comprises a second horizontal portion extending from the vertical portion and facing a second surface of the one of the semiconductor patterns, and the second surface of the one of the semiconductor patterns is opposite to the first surface of the one of the semiconductor patterns.
3. The semiconductor memory device of claim 2 , further comprising a first insulating layer and a second insulating layer that is spaced apart from the first insulating layer in the vertical direction,
wherein the first and second horizontal portions of the gate electrode and one of the bit lines are between the first and second insulating layers.
4. The semiconductor memory device of claim 2 , wherein the one of the semiconductor patterns comprises a channel region, and
wherein the first and second horizontal portions of the gate electrode are both configured to function as a gate of the channel region.
5. The semiconductor memory device of claim 2 , wherein the second surface of the one of the semiconductor patterns faces the substrate.
6. The semiconductor memory device of claim 1 , wherein the first horizontal portion overlaps the one of the semiconductor patterns.
7. The semiconductor memory device of claim 1 , wherein the one of the semiconductor patterns comprises:
a first impurity region electrically connected to one of the bit lines;
a second impurity region electrically connected to the first electrode; and
a channel region between the first and second impurity regions, and
wherein the vertical portion extends through the channel region.
8. The semiconductor memory device of claim 7 , wherein the channel region surrounds the vertical portion.
9. The semiconductor memory device of claim 1 , wherein the plurality of layers comprise a first layer comprising a first semiconductor pattern and a second layer comprising a second semiconductor pattern, and the first layer is between the substrate and the second layer, and
a first width of the first semiconductor pattern in the first direction is wider than a second width of the second semiconductor pattern in the first direction.
10. The semiconductor memory device of claim 9 , wherein a third width of the vertical portion adjacent to the first semiconductor pattern is narrower than a fourth width of the vertical portion adjacent to the second semiconductor pattern.
11. A semiconductor memory device comprising:
a plurality of layers sequentially stacked on a substrate in a vertical direction, each of the plurality of layers comprising a bit line extending in a first direction and a semiconductor pattern extending from the bit line in a second direction that traverses the first direction;
a gate electrode extending through the plurality of layers;
a data storing element electrically connected to one of the semiconductor patterns; and
a first insulating layer and a second insulating layer that is spaced apart from the first insulating layer in the vertical direction,
wherein the gate electrode comprises:
a vertical portion extending through the semiconductor patterns;
a first horizontal portion extending from the vertical portion and facing a first surface of the one of the semiconductor patterns; and
a second horizontal portion extending from the vertical portion and facing a second surface of the one of the semiconductor patterns, wherein the second surface of the one of the semiconductor patterns is opposite to the first surface of the one of the semiconductor patterns, and
wherein the first and second horizontal portions of the gate electrode and one of the bit lines are between the first and second insulating layers.
12. The semiconductor memory device of claim 11 , wherein the data storing element comprises:
a first electrode electrically connected to the one of the semiconductor patterns;
a second electrode on the first electrode; and
a dielectric layer between the first electrode and the second electrode.
13. The semiconductor memory device of claim 11 , wherein the first horizontal portion overlaps the one of the semiconductor patterns that overlaps the second horizontal portion.
14. The semiconductor memory device of claim 11 , wherein the one of the semiconductor patterns comprises:
a first impurity region electrically connected to one of the bit lines;
a second impurity region electrically connected to the data storing element; and
a channel region between the first and second impurity regions, and
wherein the vertical portion extends through the channel region.
15. A semiconductor memory device comprising:
a bit line extending on a substrate in a first direction;
a semiconductor pattern extending in a second direction that traverses the first direction, the semiconductor pattern comprising a first impurity region, a second impurity region, and a channel region between the first and second impurity regions, the first impurity region being electrically connected to the bit line;
a gate electrode comprising a vertical portion extending through the channel region of the semiconductor pattern and a first horizontal portion extending from the vertical portion and facing a first surface of the semiconductor pattern; and
a data storing element electrically connected to the second impurity region of the semiconductor pattern,
wherein the channel region surrounds the vertical portion of the gate electrode.
16. The semiconductor memory device of claim 15 , wherein the semiconductor pattern is spaced apart from the substrate, and
the semiconductor pattern has a bar-shape extending in the second direction, when viewed in a plan view.
17. The semiconductor memory device of claim 15 , wherein the gate electrode further comprises a second horizontal portion extending from the vertical portion and facing a second surface of the semiconductor pattern opposite to the first surface of the semiconductor pattern.
18. The semiconductor memory device of claim 17 , wherein the second surface of the semiconductor pattern faces the substrate.
19. The semiconductor memory device of claim 17 , further comprising a first insulating layer and a second insulating layer that is spaced apart from the first insulating layer in a vertical direction,
wherein the first and second horizontal portions of the gate electrode are between the first and second insulating layers.
20. The semiconductor memory device of claim 15 , wherein the data storing element comprises:
a first electrode electrically connected to the second impurity region;
a second electrode on the first electrode; and
a dielectric layer between the first electrode and the second electrode.