Dual-gated memtransistor crossbar array, fabricating methods and applications of same

1. A memtransistor, comprising:

a bottom gate electrode;

a bottom dielectric layer formed on the bottom gate electrode layer;

a polycrystalline monolayer film formed of an atomically thin material disposed on the bottom dielectric layer, wherein the atomically thin material comprises two-dimensional (2D) semiconductor material, wherein the 2D semiconductor material comprises monochalcogenides comprising InSe or GaTe, or black phosphorus (BP), wherein the polycrystalline monolayer film contains grains having an average grain size of about 1 μm 2 ;

a source electrode and a drain electrode spatial-apart formed on the bottom dielectric layer such that the polycrystalline monolayer film is disposed between the source electrode and the drain electrode to define a channel in the polycrystalline monolayer film therebetween;

a top dielectric layer formed on the polycrystalline monolayer film and extended over the source electrode and the drain electrode, such that each of the source electrode and the drain electrode is disposed between the bottom dielectric layer and the top dielectric layer; and

a top gate electrode formed on the top dielectric layer,

wherein the top gate electrode and the bottom gate electrode are capacitively coupled with the channel; and

wherein the memtransistor is a dual gated memtransistor characterized with a switching ratio between a low resistance state (LRS) and a high resistance state (HRS), wherein the switching ratio is a ratio of current (I LRS ) of the dual gated memtransistor at the LRS to that (I HRS ) of the dual gated memtransistor at the HRS, and wherein the dual gated memtransistor is configured such that the switching ratio increases with increasing a voltage of the bottom gate electrode.

2. The memtransistor of claim 1 , wherein the top gate electrode and the bottom gate electrode and the source and drain electrodes comprise a same conductive material or different conductive materials.

3. The memtransistor of claim 2 , wherein each of the top gate electrode and the bottom gate electrode and the source and drain electrodes is formed of gold (Au), titanium (Ti), aluminum (Al), nickel (Ni), chromium (Cr), and other conductive materials.

4. The memtransistor of claim 2 , wherein the bottom gate electrode is formed of doped silicon (Si).

5. The memtransistor of claim 1 , wherein the top dielectric layer and the bottom dielectric layer comprise a same dielectric material or different dielectric materials.

6. The memtransistor of claim 5 , wherein the top dielectric layer is formed of Al 2 O 3 , HfO 2 , ZrO 2 , or ZnO.

7. The memtransistor of claim 5 , wherein the bottom dielectric layer is formed of SiO 2 , or dielectrics including alumina, hafnia, or zirconia.

8. The memtransistor of claim 1 , wherein the memtransistor is configured to have bipolar resistive switching characteristics at different biases applied to the bottom gate electrode with the top gate electrode left floating.

9. The memtransistor of claim 1 , wherein the memtransistor is configured to have a memristive loop with minimal bottom gate bias hysteresis.

10. The memtransistor of claim 1 , wherein the memtransistor is configured such that both long-term potentiation (LTP) and long-term depression (LTD) are operably modulated as a function of a gate bias during writing, while an output current during reading is operably controlled as a function of the gate bias during reading without affecting an intrinsic state of the memtransistor.

11. A circuitry, comprising one or more memtransistors according to claim 1 .

12. An electronic device, comprising one or more memtransistors according to claim 1 .

13. A crossbar array comprised of M columns and N rows of memtransistors, each of M and N being an integer greater than zero, comprising:

a bottom gate electrode layer;

a bottom dielectric layer formed on the bottom gate electrode layer;

a polycrystalline monolayer film formed of an atomically thin material formed on the bottom dielectric layer, wherein the atomically thin material comprises two-dimensional (2D) semiconductor material, wherein the polycrystalline monolayer film contains grains having an average grain size of about 1 μm 2 ;

M+1 source-drain electrodes spatial-apart formed on the polycrystalline monolayer film along a column direction, wherein the polycrystalline monolayer film is patterned according to the M+1 source-drain electrodes to define M columns and N rows of channels therein, such that each two neighboring source-drain electrodes are coupled with N channels of a respective channel column between said two neighboring source-drain electrodes;

a top dielectric layer formed on the polycrystalline monolayer film and extended over the M+1 source-drain electrodes, such that each of the M+1 source-drain electrodes is disposed between the bottom dielectric layer and the top dielectric layer; and

N top gate electrodes formed on the top dielectric layer, crossing over the M+1 source-drain electrodes along a row direction, such that each top gate electrode is capacitively coupled with M channels of a respective channel row,

wherein each memtransistor is a dual gated memtransistor characterized with a switching ratio between a low resistance state (LRS) and a high resistance state (HRS), wherein the switching ratio is a ratio of current (I LRS ) of the dual gated memtransistor at the LRS to that (I HRS ) of the dual gated memtransistor at the HRS, and wherein each dual gated memtransistor is configured such that the switching ratio increases with increasing a voltage of the bottom gate electrode.

14. The crossbar array of claim 13 , wherein the 2D semiconductor material comprises MoS 2 , MoSe 2 , WS 2 , WSe 2 , InSe, GaTe, black phosphorus (BP), or related two-dimensional materials.

15. The crossbar array of claim 13 , wherein the bottom gate electrode layer comprises a globe bottom gate electrode capacitively coupled with the M columns and the N rows of channels.

16. The crossbar array of claim 13 , wherein the bottom gate electrode layer comprises N bottom gate electrodes crossing over the M+1 source-drain electrodes along the row direction, such that each bottom gate electrode is capacitively coupled with M channels of a respective channel row.

17. The crossbar array of claim 13 , wherein the top gate electrodes and the bottom gate electrode layer and the source-drain electrodes comprise a same conductive material or different conductive materials.

18. The crossbar array of claim 17 , wherein each of the top gate electrode and the bottom gate electrode and the source-drain electrodes is formed of gold (Au), titanium (Ti), aluminum (Al), nickel (Ni), chromium (Cr), and other conductive materials.

19. The crossbar array of claim 17 , wherein the bottom gate electrodes are formed of doped silicon (Si).

20. The crossbar array of claim 13 , wherein the top dielectric layer and the bottom dielectric layer comprise a same dielectric material or different dielectric materials.

21. The crossbar array of claim 20 , wherein the top dielectric layer is formed of Al 2 O 3 , HfO 2 , ZrO 2 , or ZnO.

22. The crossbar array of claim 20 , wherein the bottom dielectric layer is formed of SiO 2 , or dielectrics including alumina, hafnia, or zirconia.

23. The crossbar array of claim 13 , wherein each memtransistor is configured to have bipolar resistive switching characteristics at different biases applied to the bottom gate electrode with the top gate electrode left floating.

24. The crossbar array of claim 13 , wherein each memtransistor is configured to have a memristive loop with minimal bottom gate bias hysteresis.

25. The crossbar array of claim 13 , wherein each memtransistor is configured such that both long-term potentiation (LTP) and long-term depression (LTD) are operably modulated as a function of a gate bias during writing, while an output current during reading is operably controlled as a function of the gate bias during reading without affecting an intrinsic state of said memtransistor.

26. The crossbar array of claim 13 , wherein the source and drain electrodes (S i /D i+1 ) are shared by neighboring memtransistors in columns i and i+1 (except i=1, M).

27. The crossbar array of claim 13 , being configured such that each memtransistor is writable and readable independently, thereby minimizing sneak current in the crossbar array.

28. The crossbar array of claim 13 , being configured such that application of a predetermined bottom gate voltage suppresses read currents without changing non-volatile memristive resistance states of the memtransistors in the crossbar array, thereby enabling isolation of the non-volatile memristive resistance states and read currents without additional elements at each node for crossbar operation in the crossbar array.

29. The crossbar array of claim 13 , wherein each memtransistor has gate tunability.

30. The crossbar array of claim 29 , wherein a linear and symmetric learning behavior that produces efficient training of an artificial neural network (ANN) is achievable by the gate tunability.

31. A circuitry, comprising one or more crossbar arrays according to claim 13 .

32. An electronic device, comprising one or more crossbar arrays according to claim 13 .

33. The memtransistor of claim 1 , wherein the memtransistor is configured to have a pinched hysteresis loop in the clockwise direction at forward bias.

34. The memtransistor of claim 33 , wherein the memtransistor is configured to have drain current at the forward bias being larger than that at reverse bias.

35. The memtransistor of claim 1 , wherein the memtransistor is configured such that a top gate voltage controls the switching ratio in a non-monotonic fashion.

36. The memtransistor of claim 1 , wherein the channel has a channel length of about 0.9 μm, and a channel width of about 0.7 μm.

37. The crossbar array of claim 13 , wherein each channel has a channel length of about 0.9 μm, and a channel width of about 0.7 μm.