Post gate dielectric processing for semiconductor device fabrication
Semiconductor device and the manufacturing method thereof are disclosed. An exemplary semiconductor device comprises a first semiconductor stack and a second semiconductor stack over a substrate, wherein each of the first and second semiconductor stacks includes semiconductor layers stacked up and separated from each other; a dummy spacer between the first and second semiconductor stacks, wherein the dummy spacer contacts a first sidewall of each semiconductor layer of the first and second semiconductor stacks; and a gate structure wrapping a second sidewall, a top surface, and a bottom surface of each semiconductor layer of the first and second semiconductor stacks.
1. A method of forming a semiconductor device, comprising:
forming a semiconductor fin over a substrate;
forming spacers over the semiconductor fin, wherein the spacers form a trench over the semiconductor fin;
depositing a high-K dielectric layer in the trench;
forming a capping layer over the high-K dielectric layer in one processing tool;
performing an annealing process to the capping layer;
removing the capping layer to expose the high-K dielectric layer; and
forming a metal gate electrode over the high-K dielectric layer,
wherein removing the capping layer includes a wet only etching process.
2. The method of claim 1 , forming the capping layer over the high-K dielectric layer includes:
depositing high-K capping material over the high-K dielectric layer in the processing tool; and
passing a processing gas, in the processing tool, over a top surface of the high-K capping material to form the capping layer.
3. The method of claim 2 , wherein the high-K capping material includes titanium nitride (TiN), tantalum nitride (TaN), or tennessine nitride (TsN).
4. The method of claim 2 , wherein the processing gas is silane (SiH 4 ) and is passed at a pressure of about 4 to 6 torr, with a flow rate of about 300 to 500 sccm and for a period of about 100 to 200 seconds.
5. The method of claim 1 , wherein a thickness ratio of the capping layer to the high-K dielectric layer is about 1.3 to about 2.3.
6. The method of claim 1 , wherein performing an annealing process to the capping layer includes performing a spike annealing process to the capping layer for a temperature of about 850° C. to about 950° C.
7. The method of claim 1 , further comprising performing an annealing process to the high-K dielectric layer after removing the capping layer.
8. The method of claim 1 , wherein the wet only etching process comprises use of hydrogen fluoride (HF), ammonium hydroxide (NH 4 OH), hydrogen peroxide (H 2 O 2 ), or water (H 2 O).
9. A method of forming a semiconductor device, comprising:
forming a semiconductor fin over a substrate;
forming spacers over the semiconductor fin, wherein the spacers forms a trench over the semiconductor fin;
forming an interfacial layer in the trench;
depositing a high-K dielectric layer over the interfacial layer;
performing an annealing process to the high-K dielectric layer;
forming a capping layer over the high-K dielectric layer in one processing tool;
performing an annealing process to the capping layer;
removing the capping layer to expose the high-K dielectric layer; and
forming a metal gate electrode over the high-K dielectric layer,
wherein removing the capping layer includes a selective wet only etching process.
10. The method of claim 9 , further comprising performing an annealing process to the interfacial layer before depositing the high-K dielectric layer.
11. The method of claim 10 , wherein the annealing process to the interfacial layer is applied in an ambiance including at least one of nitrogen, hydrogen, and ammonia.
12. The method of claim 9 , wherein forming spacers over the semiconductor fin includes:
forming a dummy gate structure over the semiconductor fin;
forming spacers along sidewalls of the dummy gate structure; and
removing the dummy gate structure to form the trench over the semiconductor fin.
13. The method of claim 9 , wherein forming the capping layer over the high-K dielectric layer includes:
depositing high-K capping material over the high-K dielectric layer in the processing tool; and
passing a processing gas, in the processing tool, to a top of the high-K capping material to form the capping layer.
14. The method of claim 9 , wherein the capping layer has a thickness of about 2 nm to about 3.5 nm.
15. The method of claim 9 , wherein the selective wet only process includes an etching step using a first etchant for about 30 to 40 seconds and an etching step using a second etchant for about 120 to 210 seconds.
16. The method of claim 15 , wherein the first etchant is diluted hydrogen fluoride (HF), the second etchant is ammonium hydroxide (NH 4 OH), hydrogen peroxide (H 2 O 2 ), or water (H 2 O).
17. A method of forming a semiconductor device, comprising:
forming a semiconductor fin over a substrate;
forming spacers over the semiconductor fin, wherein the spacers forms a trench over the semiconductor fin;
depositing a high-K dielectric layer in the trench;
depositing a high-K capping material over the high-K dielectric layer;
passing a processing gas over a top surface of the high-K capping material to form a capping layer;
performing an annealing process to the capping layer;
removing the capping layer to expose the high-K dielectric layer; and
forming a metal gate electrode over the high-K dielectric layer,
wherein removing the capping layer includes a selective wet only etching process and the selective wet only etching process comprises use of hydrogen fluoride (HF), ammonium hydroxide (NH 4 OH), hydrogen peroxide (H 2 O 2 ), or water (H 2 O).
18. The method of claim 17 , wherein the high-K capping material is deposited by an atomic layer deposition (ALD) process.
19. The method of claim 17 , further comprising performing an annealing process to the high-K dielectric layer.
20. The method of claim 17 , wherein the steps of depositing the high-K capping material over the high-K dielectric layer and passing the processing gas over a top surface of the high-K capping material are performed in a same tool.