Semiconductor device and method for fabricating the same
A semiconductor device includes a substrate, a gate structure on the substrate, and a gate contact in the gate structure. The gate structure includes a gate electrode extending in a first direction and a gate capping pattern on the gate electrode. The gate contact is connected to the gate electrode. The gate electrode includes a protrusion extending along a boundary between the gate contact and the gate capping pattern.
1. A semiconductor device comprising:
a substrate;
a gate structure on the substrate, the gate structure including a gate electrode extending in a first direction, a gate capping pattern on the gate electrode, and a gate spacer on a sidewall of the gate electrode extending in the first direction, the gate electrode including a protrusion, the first direction extending parallel to an upper surface of the substrate; and
a gate contact in the gate structure and connected to the gate electrode, the gate contact positioned so the protrusion extends along a boundary between the gate contact and the gate capping pattern,
wherein the gate capping pattern overlaps the protrusion in the first direction,
wherein an inner wall of the protrusion is in contact with the gate contact, and
wherein at least a part of the gate contact in the gate structure is in contact with the gate spacer.
2. The semiconductor device of claim 1 , wherein the protrusion of the gate electrode covers at least a part of a side wall of the gate contact.
3. The semiconductor device of claim 2 , wherein
the side wall of the gate contact includes a first portion covered with the protrusion of the gate electrode and a second portion covered with the gate capping pattern.
4. The semiconductor device of claim 1 , wherein
the gate capping pattern includes a lower surface facing the substrate,
the gate capping pattern includes an upper surface that is opposite the lower surface of the gate capping pattern, and
an upper surface of the gate contact does not protrude upward from the upper surface of the gate capping pattern.
5. The semiconductor device of claim 1 , further comprising:
a wiring structure on the gate contact, wherein
the wiring structure includes a via and a wiring pattern connected to the via, and
the via is directly connected to the gate contact.
6. The semiconductor device of claim 1 , wherein
the protrusion of the gate electrode includes a first side wall facing the gate contact and a second side wall opposite the first side wall, and
the first side wall of the protrusion of the gate electrode includes a curved surface.
7. The semiconductor device of claim 6 , wherein a height of the first side wall of the protrusion of the gate electrode is the same as a height of the second side wall of the protrusion of the gate electrode.
8. The semiconductor device of claim 6 , wherein a height of the first side wall of the protrusion of the gate electrode is greater than a height of the second side wall of the protrusion of the gate electrode.
9. The semiconductor device of claim 6 , wherein a height of the first side wall of the protrusion of the gate electrode is smaller than a height of the second side wall of the protrusion of the gate electrode.
10. The semiconductor device of claim 1 , wherein
the gate structure includes a gate contact hole,
the gate contact includes a contact barrier film and a contact filling film,
the contact barrier film extends along a profile of the gate contact hole, and
the contact filling film fills the gate contact hole on the contact barrier film.
11. The semiconductor device of claim 10 , wherein the contact barrier film includes at least one of tantalum (Ta), tantalum nitride (TaN), titanium (Ti), titanium nitride (TiN), ruthenium (Ru), cobalt (Co), nickel (Ni), nickel boron (NiB), tungsten (W), tungsten nitride (WN), tungsten carbonitride (WCN), zirconium (Zr), zirconium nitride (ZrN), vanadium (V), vanadium nitride (VN), niobium (Nb), niobium nitride (NbN), platinum (Pt), iridium (Ir), rhodium (Rh), and a two-dimensional (2D) material.
12. The semiconductor device of claim 1 , wherein
the substrate includes a multi-channel active pattern,
the multi-channel active pattern extends in a second direction,
the gate structure intersects the multi-channel active pattern, and
the second direction crosses the first direction and extends parallel to the upper surface of the substrate.
13. The semiconductor device of claim 1 , wherein
the gate structure includes a gate insulating film between the substrate and the gate electrode, and
the gate insulating film includes boron nitride.
14. A semiconductor device comprising:
a substrate including an active region and a field region,
the substrate including a multi-channel active pattern in the active region, the multi-channel active pattern extending in a first direction;
a gate structure intersecting the multi-channel active pattern,
the gate structure including a gate electrode extending in a second direction, a gate capping pattern extending along an upper surface of the gate electrode, and a gate spacer on a side wall of the gate electrode extending in the second direction,
the gate electrode including a protrusion including an inner wall and an outer wall,
the inner wall of the protrusion having a concave shape,
the outer wall being defined along a periphery of the inner wall;
a source/drain pattern adjacent to at least one side of the gate structure and connected to the multi-channel active pattern;
a gate contact on the active region of the substrate and connected to the gate electrode, at least a part of the gate contact being in a pocket defined by the inner wall of the protrusion of the gate electrode; and
a source/drain contact on the active region of the substrate and connected to the source/drain pattern, and
wherein the inner wall is contact with the gate contact,
wherein the outer wall is contact with the gate capping pattern, and
wherein at least a part of the gate contact is in contact with the gate spacer.
15. The semiconductor device of claim 14 , wherein
an outer wall of the protrusion of the gate electrode borders the gate spacer and the gate capping pattern.
16. The semiconductor device of claim 14 , wherein the protrusion of the gate electrode extends up to an upper surface of the gate contact.
17. The semiconductor device of claim 14 , further comprising:
a wiring structure on the gate structure, wherein
wherein the wiring structure includes a via and a wiring pattern connected to the via, and
the via is directly connected to the gate contact.
18. The semiconductor device of claim 14 , wherein the protrusion of the gate electrode extends in a thickness direction of the substrate.
19. The semiconductor device of claim 18 , wherein the inner wall of the protrusion of the gate electrode directly joins the outer wall of the protrusion of the gate electrode.
20. The semiconductor device of claim 14 , wherein an upper surface of the gate contact is level with an upper surface of the gate capping pattern.