Kickback compensation for a capacitively driven comparator
An analog-to-digital converter (ADC) includes a comparator, a voltage reference circuit, a first capacitive digital-to-analog converter (CDAC), and a second CDAC. The first CDAC includes a plurality of capacitors. Each of the capacitors of the first CDAC includes a top plate coupled to a first input of the comparator, and a bottom plate switchably coupled to an output of the voltage reference circuit. The second CDAC includes a plurality of capacitors. Each of the capacitors of the second CDAC includes a top plate coupled to a second input of the comparator, and a bottom plate switchably coupled to a ground reference.
1. An analog-to-digital converter (ADC), comprising:
a comparator having a first input and a second input;
a voltage reference circuit having an output;
a first capacitive digital-to-analog converter (CDAC) comprising:
a plurality of capacitors, each comprising:
a top plate coupled to the first input of the comparator; and
a bottom plate switchably coupled to the output of the voltage reference circuit, a first ground reference or an analog input;
a second CDAC comprising:
a plurality of capacitors, each comprising:
a top plate coupled to the second input of the comparator; and
a bottom plate switchably coupled to a second ground reference, a third ground reference, or the analog input.
2. The ADC of claim 1 , wherein:
the first CDAC comprises a first plurality of switches, each of the switches configured to switchably couple the bottom plate of one of the capacitors of the first CDAC to the output of the voltage reference circuit;
the second CDAC comprises a first plurality of switches, each of the switches configured to switchably couple the bottom plate of one of the capacitors of the second CDAC to the second ground reference.
3. The ADC of claim 2 , wherein:
the first CDAC comprises a second plurality of switches, each of the switches configured to switchably couple the bottom plate of one of the capacitors of the first CDAC to the first ground reference;
the second CDAC comprises a second plurality of switches, each of the switches configured to switchably couple the bottom plate of one of the capacitors of the second CDAC to the second ground reference.
4. The ADC of claim 3 , wherein the second plurality of switches of the second CDAC is configured to couple capacitors of the second CDAC to the third ground reference in conjunction with the second plurality of switches of the first CDAC being set to couple capacitors of the first CDAC to the first ground reference.
5. The ADC of claim 2 , wherein the first plurality of switches of the second CDAC is configured to couple capacitors of the second CDAC to the second ground reference in conjunction with the first plurality of switches of the first CDAC being set to couple capacitors of the first CDAC to the output of the voltage reference circuit.