Semiconductor device including guard rings

1. A semiconductor device comprising:

a substrate;

a guard ring disposed on the substrate and adjacent to an edge of the substrate;

an integrated circuit structure surrounded by the guard ring and disposed on the substrate; and

an insulating material structure disposed on a side surface of the guard ring,

wherein the integrated circuit structure includes a circuit active fin disposed on the substrate, a gate structure intersecting the circuit active fin, a source or drain region on the circuit active fin adjacent to a side surface of the gate structure, a circuit contact structure disposed on the source or drain region, and a circuit interconnection structure disposed on the circuit contact structure,

wherein the guard ring includes a plurality of guard active structures on the substrate, a plurality of guard contact structures disposed on each of the plurality of guard active structures, and a guard interconnection structure disposed on a pair of guard contact structures adjacent to each other, among the plurality of guard contact structures,

wherein the source or drain region is disposed between the circuit contact structure and the circuit active fin,

wherein each of the plurality of guard active structures includes a plurality of guard active fins spaced apart from each other,

wherein in each of the plurality of guard active structures, upper surfaces of a first group of the plurality of guard active fins at least partially overlap the insulating material structure in a vertical direction, and upper surfaces of a second group of the plurality of guard active fins are in contact with the plurality of guard contact structures,

wherein the second group of the plurality of guard active fins are disposed in between the first group of the plurality of guard active fins,

wherein an upper surface of a guard active fin in the first group is disposed on a higher level than an upper surface of a guard active fin in the second group, and

wherein the vertical direction is perpendicular to an upper surface of the substrate.

2. The semiconductor device of claim 1 , wherein the guard interconnection structure at least partially overlaps the pair of guard contact structures and the insulating material structure, wherein the insulating material structure is disposed between the pair of guard contact structures, in the vertical direction.

3. The semiconductor device of claim 1 , wherein each of the plurality of guard contact structures has a width greater than a width of each of the plurality of guard active fins, and

wherein each of the plurality of guard contact structures is in contact with one of a pair of guard active fins adjacent to each other and is spaced apart from the other one of the pair of guard active fins.

4. A semiconductor device comprising:

a substrate;

an integrated circuit structure disposed on the substrate;

a guard ring disposed on the substrate at least partially surrounding the integrated circuit structure; and

an insulating material structure on a side surface of the guard ring,

wherein the integrated circuit structure includes a circuit active fin disposed on the substrate, a gate structure intersecting the circuit active fin, a source or drain region disposed on the circuit active fin adjacent to a side surface of the gate structure, a circuit contact structure disposed on the source or drain region, and a circuit interconnection structure disposed on the circuit contact structure,

wherein the guard ring includes a guard active structure including a plurality of guard active fins spaced apart from each other and disposed on the substrate, a plurality of guard contact structures spaced apart from each other, and a guard interconnection structure disposed on the plurality of guard contact structures,

wherein the plurality of guard contact structures are disposed on the guard active structure,

wherein in the guard active structure, a second group of the plurality of guard active fins are disposed in between a first group of the plurality of guard active fins,

wherein an upper surface of a guard active fin in the first group is disposed on a higher level than an upper surface of a guard active fin in the second group,

wherein the source or drain region is disposed between the circuit contact structure and the circuit active fin,

wherein the guard interconnection structure is in contact with the plurality of guard contact structures,

wherein the guard active structure is in contact with the plurality of guard contact structures, and

wherein the plurality of guard active fins include a pair of guard active fins adjacent to each other, and one of the pair of guard active fins is in contact with one of the plurality of guard contact structures and the other one of the pair of guard active fins is not in contact with the plurality of guard contact structures.

5. The semiconductor device of claim 4 , wherein the insulating material structure comprises:

an isolation region disposed on side surfaces of the plurality of guard active fins;

a protective layer disposed on the isolation region; and

an interlayer insulating layer disposed on the protective layer,

wherein the protective layer covers an upper surface of a guard active fin of the plurality of guard active fins, which is not in contact with the plurality of guard contact structures, among the plurality of guard active fins.

6. The semiconductor device of claim 4 , wherein the second group of the plurality of guard active fins overlap the plurality of guard contact structures, and

wherein the first group of the plurality of guard active fins are excluded from overlapping the plurality of guard contact structures.

7. A semiconductor device comprising:

a substrate;

an integrated circuit structure disposed on the substrate;

a guard ring disposed on the substrate at least partially surrounding the integrated circuit structure; and

an insulating material structure on a side surface of the guard ring,

wherein the integrated circuit structure includes a circuit active fin disposed on the substrate, a gate structure intersecting the circuit active fin, a source or drain region disposed on the circuit active fin adjacent to a side surface of the gate structure, a circuit contact structure disposed on the source or drain region, and a circuit interconnection structure disposed on the circuit contact structure,

wherein the guard ring includes a guard active structure including a plurality of guard active fins spaced apart from each other and disposed on the substrate, a plurality of guard contact structures spaced apart from each other, and a guard interconnection structure disposed on the plurality of guard contact structures,

wherein the source or drain region is disposed between the circuit contact structure and the circuit active fin,

wherein the guard interconnection structure is in contact with the plurality of guard contact structures,

wherein the guard active structure is in contact with the plurality of guard contact structures,

wherein the plurality of guard active fins include a pair of guard active fins adjacent to each other, and one of the pair of guard active fins is in contact with one of the plurality of guard contact structures and the other one of the pair of guard active fins is not in contact with the plurality of guard contact structures,

wherein both side surfaces of the guard interconnection structure, opposing each other, at least partially overlap upper surfaces of the plurality of guard contact structures that are adjacent to each other, in a vertical direction,

wherein an area between the both side surfaces of the guard interconnection structure at least partially overlaps the insulating material structure in the vertical direction, and

wherein the vertical direction is perpendicular to an upper surface of the substrate.